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Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

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Aelbahri 2023-01-11 15:37:38 +01:00
commit b6d494781e
2 changed files with 62 additions and 66 deletions
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10
src/simulator/machine.rs
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@ -23,7 +23,7 @@ impl Machine {
value = (value << 32) + value; value = (value << 32) + value;
for item in &mut shiftmask { for item in &mut shiftmask {
*item = value; *item = value;
value = value >> 1; value >>= 1;
} }
Machine { Machine {
@ -44,7 +44,7 @@ impl Machine {
/// - **address** in the memory to read /// - **address** in the memory to read
pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
if size != 1 && size != 2 && size != 4 && size != 8 { if size != 1 && size != 2 && size != 4 && size != 8 {
println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
} }
let mut ret : u64 = machine.main_memory[address] as u64; let mut ret : u64 = machine.main_memory[address] as u64;
@ -202,8 +202,7 @@ impl Machine {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
}, },
RISCV_OPI_SLTI => { RISCV_OPI_SLTI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64;
if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 };
}, },
RISCV_OPI_XORI => { RISCV_OPI_XORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
@ -378,6 +377,5 @@ impl Machine {
#[cfg(test)] #[cfg(test)]
mod test { mod test {
use super::Machine;
} }

116
src/simulator/print.rs
View File

@ -163,22 +163,22 @@ pub const RISCV_ATOM_MINU: u8 = 0x18;
pub const RISCV_ATOM_MAXU: u8 = 0x1c; pub const RISCV_ATOM_MAXU: u8 = 0x1c;
const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"];
const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
// Register name mapping // Register name mapping
const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"]; "t3", "t4", "t5", "t6"];
const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
"ft8", "ft9", "ft10", "ft11"]; "ft8", "ft9", "ft10", "ft11"];
@ -193,53 +193,51 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
RISCV_OP => { RISCV_OP => {
let name: &str; let name: &str;
if ins.funct7 == 1 { // Use mul array if ins.funct7 == 1 { // Use mul array
name = names_mul[ins.funct3 as usize] name = NAMES_MUL[ins.funct3 as usize]
} else { } else if ins.funct3 == RISCV_OP_ADD {
if ins.funct3 == RISCV_OP_ADD { // Add or Sub
// Add or Sub if ins.funct7 == RISCV_OP_ADD_ADD {
if ins.funct7 == RISCV_OP_ADD_ADD { name = "add";
name = "add";
} else {
name = "sub";
}
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else { } else {
name = names_op[ins.funct3 as usize]; name = "sub";
} }
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else {
name = NAMES_OP[ins.funct3 as usize];
} }
format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
}, },
RISCV_OPI => { RISCV_OPI => {
// SHAMT OR IMM // SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI { if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI { if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("slrii\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
} else { } else {
format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
} }
} else if ins.funct3 == RISCV_OPI_SLLI { } else if ins.funct3 == RISCV_OPI_SLLI {
format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt)
} else { } else {
format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
} }
}, },
RISCV_LUI => { RISCV_LUI => {
format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12) format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12)
}, },
RISCV_AUIPC => { RISCV_AUIPC => {
format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12) format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12)
}, },
RISCV_JAL => { RISCV_JAL => {
if ins.rd == 0 { if ins.rd == 0 {
format!("j\t{}", ins.imm31_12.to_string()) format!("j\t{}", ins.imm31_12)
} else { } else {
format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) format!("jal\t{}, {:X}", REG_X[rd], (pc - 4 + ins.imm21_1_signed))
} }
}, },
RISCV_JALR => { RISCV_JALR => {
@ -250,50 +248,48 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
format!("jr\t{:X}", ins.imm31_12) format!("jr\t{:X}", ins.imm31_12)
} }
} else { } else {
format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1])
} }
}, },
RISCV_BR => { RISCV_BR => {
format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed)
}, },
RISCV_LD => { RISCV_LD => {
format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) format!("{}\t{}, {}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
}, },
RISCV_ST => { RISCV_ST => {
format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) format!("{}\t{}, {}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1])
}, },
RISCV_OPIW => { RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW { if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("srlwi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else { } else {
format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("srawi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} }
} else if ins.funct3 == RISCV_OPIW_SLLIW { } else if ins.funct3 == RISCV_OPIW_SLLIW {
format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else { } else {
format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
} }
}, },
RISCV_OPW => { RISCV_OPW => {
if ins.funct7 == 1 { if ins.funct7 == 1 {
format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else { } else if ins.funct3 == RISCV_OP_ADD {
if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { format!("addw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else {
format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
}
} else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else {
format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
}
} else { } else {
format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("subw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} }
} else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else {
format!("{}\t{}, {}, {}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} }
}, },
RISCV_SYSTEM => { RISCV_SYSTEM => {
@ -307,6 +303,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
#[cfg(test)] #[cfg(test)]
mod test { mod test {
#![allow(clippy::unusual_byte_groupings)]
use crate::simulator::{decode, print}; use crate::simulator::{decode, print};