From 9748b0f2dc0feae6b9f4c866a15730e5cc2b361b Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 19 Oct 2022 16:39:38 +0200 Subject: [PATCH 001/128] decode & struct Instruction --- Cargo.lock | 7 +++++++ src/decode.rs | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/main.rs | 3 +++ 3 files changed, 67 insertions(+) create mode 100644 Cargo.lock create mode 100644 src/decode.rs diff --git a/Cargo.lock b/Cargo.lock new file mode 100644 index 0000000..1e08526 --- /dev/null +++ b/Cargo.lock @@ -0,0 +1,7 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 3 + +[[package]] +name = "burritos" +version = "0.1.0" diff --git a/src/decode.rs b/src/decode.rs new file mode 100644 index 0000000..ed21275 --- /dev/null +++ b/src/decode.rs @@ -0,0 +1,57 @@ +pub struct Instruction { + value : u64, + + opcode : u8, + rs1 : u8, + rs2 : u8, + rs3 : u8, + rd : u8, + funct7 : u8, + funct7_smaller : u8, + funct3 : u8, + shamt : u8, + + imm12_I : u16, + imm12_S : u16, + + imm12_I_signed : i16, + imm12_S_signed : i16, + imm13 : i16, + imm13_signed : i16, + + imm31_12 : u32, + imm21_1 : u32, + + imm31_12_signed : i32, + imm21_1_signed : i32, +} + +pub fn decode(val : u64) -> Instruction { + Instruction { + value : val, + + opcode : 0, + rs1 : 0, + rs2 : 0, + rs3 : 0, + rd : 0, + funct7 : 0, + funct7_smaller : 0, + funct3 : 0, + shamt : 0, + + imm12_I : 0, + imm12_S : 0, + + imm12_I_signed : 0, + imm12_S_signed : 0, + imm13 : 0, + imm13_signed : 0, + + imm31_12 : 0, + imm21_1 : 0, + + imm31_12_signed : 0, + imm21_1_signed : 0, + } +} \ No newline at end of file diff --git a/src/main.rs b/src/main.rs index e7a11a9..9c521f7 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,3 +1,6 @@ +mod decode; + fn main() { + let instr = decode::decode(98); println!("Hello, world!"); } From cfb0a8e176379ade0302ccf2f5f0ac487dfdbea2 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 19 Oct 2022 17:23:41 +0200 Subject: [PATCH 002/128] decode (recquire tests) --- src/decode.rs | 121 ++++++++++++++++++++++++++++++++------------------ src/main.rs | 2 +- 2 files changed, 78 insertions(+), 45 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index ed21275..80ac041 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -1,57 +1,90 @@ pub struct Instruction { - value : u64, + pub value : u64, - opcode : u8, - rs1 : u8, - rs2 : u8, - rs3 : u8, - rd : u8, - funct7 : u8, - funct7_smaller : u8, - funct3 : u8, - shamt : u8, + pub opcode : u8, + pub rs1 : u8, + pub rs2 : u8, + pub rs3 : u8, + pub rd : u8, + pub funct7 : u8, + pub funct7_smaller : u8, + pub funct3 : u8, + pub shamt : u8, - imm12_I : u16, - imm12_S : u16, + pub imm12_I : u16, + pub imm12_S : u16, - imm12_I_signed : i16, - imm12_S_signed : i16, - imm13 : i16, - imm13_signed : i16, + pub imm12_I_signed : i16, + pub imm12_S_signed : i16, + pub imm13 : i16, + pub imm13_signed : i16, - imm31_12 : u32, - imm21_1 : u32, + pub imm31_12 : u32, + pub imm21_1 : u32, - imm31_12_signed : i32, - imm21_1_signed : i32, + pub imm31_12_signed : i32, + pub imm21_1_signed : i32, } pub fn decode(val : u64) -> Instruction { + + let value = val; + + let opcode = (val & 0x7f) as u8; + let rs1 = ((val >> 15) & 0x1f) as u8; + let rs2 = ((val >> 20) & 0x1f) as u8; + let rs3 = ((val >> 27) & 0x1f) as u8; + let rd = ((val >> 7) & 0x1f) as u8; + let funct7 = ((val >> 25) & 0x7f) as u8; + let funct7_smaller = (funct7 & 0x3e) as u8; + + let funct3 = ((val >> 12) & 0x7) as u8; + let imm12_I = ((val >> 20) & 0xfff) as u16; + let imm12_S = (((val >> 20) & 0xfe0) + ((val >> 7) & 0x1f)) as u16; + + let imm12_I_signed = if imm12_I >= 2048 { imm12_I - 4096 } else { imm12_I } as i16; + let imm12_S_signed = if imm12_S >= 2048 { imm12_S - 4096 } else { imm12_S } as i16; + + let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) + + ((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16; + let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 } as i16; + + let imm31_12 = (val & 0xfffff000) as u32; + let imm31_12_signed = imm31_12 as i32; + + let imm21_1 = ((val & 0xff000) + ((val >> 9) & 0x800) + + ((val >> 20) & 0x7fe) + ((val >> 11) & 0x100000)) as u32; + let imm21_1_signed = if imm21_1 >= 1048576 { imm21_1 - 2097152 } else { imm21_1 } as i32; + + let shamt = ((val >> 20) & 0x3f) as u8; + Instruction { - value : val, + value : value, - opcode : 0, - rs1 : 0, - rs2 : 0, - rs3 : 0, - rd : 0, - funct7 : 0, - funct7_smaller : 0, - funct3 : 0, - shamt : 0, - - imm12_I : 0, - imm12_S : 0, - - imm12_I_signed : 0, - imm12_S_signed : 0, - imm13 : 0, - imm13_signed : 0, - - imm31_12 : 0, - imm21_1 : 0, - - imm31_12_signed : 0, - imm21_1_signed : 0, + opcode : opcode, + rs1 : rs1, + rs2 : rs2, + rs3 : rs3, + rd : rd, + funct7 : funct7, + funct7_smaller : funct7_smaller, + + funct3 : funct3, + imm12_I : imm12_I, + imm12_S : imm12_S, + + imm12_I_signed : imm12_I_signed, + imm12_S_signed : imm12_S_signed, + + imm13 : imm13, + imm13_signed : imm13_signed, + + imm31_12 : imm31_12, + imm31_12_signed : imm31_12_signed, + + imm21_1 : imm21_1, + imm21_1_signed : imm21_1_signed, + + shamt : shamt } } \ No newline at end of file diff --git a/src/main.rs b/src/main.rs index 9c521f7..16cda16 100644 --- a/src/main.rs +++ b/src/main.rs @@ -2,5 +2,5 @@ mod decode; fn main() { let instr = decode::decode(98); - println!("Hello, world!"); + println!("Hello, world! opcode : {}", instr.opcode); } From 0c5012c16217a96aa9fb058a7a1f6b1c66b975eb Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 26 Oct 2022 13:31:40 +0200 Subject: [PATCH 003/128] add print.rs file --- src/print.rs | 267 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) create mode 100644 src/print.rs diff --git a/src/print.rs b/src/print.rs new file mode 100644 index 0000000..13a54d0 --- /dev/null +++ b/src/print.rs @@ -0,0 +1,267 @@ +pub struct Instruction { + value : u64, + + opcode : u8, + rs1 : u8, + rs2 : u8, + rs3 : u8, + rd : u8, + funct7 : u8, + funct7_smaller : u8, + funct3 : u8, + shamt : u8, + + imm12_I : u16, + imm12_S : u16, + + imm12_I_signed : i16, + imm12_S_signed : i16, + imm13 : i16, + imm13_signed : i16, + + imm31_12 : u32, + imm21_1 : u32, + + imm31_12_signed : i32, + imm21_1_signed : i32, +} + +const RISCV_LUI: u8 = 0x37; +const RISCV_AUIPC: u8 = 0x17; +const RISCV_JAL: u8 = 0x6f; +const RISCV_JALR: u8 = 0x67; +const RISCV_BR: u8 = 0x63; +const RISCV_LD: u8 = 0x3; +const RISCV_ST: u8 = 0x23; +const RISCV_OPI: u8 = 0x13; +const RISCV_OP: u8 = 0x33; +const RISCV_OPIW: u8 = 0x1b; +const RISCV_OPW: u8 = 0x3b; + + +const RISCV_BR_BEQ: u8 = 0x0; +const RISCV_BR_BNE: u8 = 0x1; +const RISCV_BR_BLT: u8 = 0x4; +const RISCV_BR_BGE: u8 = 0x5; +const RISCV_BR_BLTU: u8 = 0x6; +const RISCV_BR_BGEU: u8 = 0x7; + +const RISCV_LD_LB: u8 = 0x0; +const RISCV_LD_LH: u8 = 0x1; +const RISCV_LD_LW: u8 = 0x2; +const RISCV_LD_LD: u8 = 0x3; +const RISCV_LD_LBU: u8 = 0x4; +const RISCV_LD_LHU: u8 = 0x5; +const RISCV_LD_LWU: u8 = 0x6; + +const RISCV_ST_STB: u8 = 0x0; +const RISCV_ST_STH: u8 = 0x1; +const RISCV_ST_STW: u8 = 0x2; +const RISCV_ST_STD: u8 = 0x3; + +const RISCV_OPI_ADDI: u8 = 0x0; +const RISCV_OPI_SLTI: u8 = 0x2; +const RISCV_OPI_SLTIU: u8 = 0x3; +const RISCV_OPI_XORI: u8 = 0x4; +const RISCV_OPI_ORI: u8 = 0x6; +const RISCV_OPI_ANDI: u8 = 0x7; +const RISCV_OPI_SLLI: u8 = 0x1; +const RISCV_OPI_SRI: u8 = 0x5; +const RISCV_OPI_SRI_SRAI: u8 = 0x20; +const RISCV_OPI_SRI_SRLI: u8 = 0x0; + +const RISCV_OP_ADD: u8 = 0x0; +const RISCV_OP_SLL: u8 = 0x1; +const RISCV_OP_SLT: u8 = 0x2; +const RISCV_OP_SLTU: u8 = 0x3; +const RISCV_OP_XOR: u8 = 0x4; +const RISCV_OP_SR: u8 = 0x5; +const RISCV_OP_OR: u8 = 0x6; +const RISCV_OP_AND: u8 = 0x7; +const RISCV_OP_ADD_ADD: u8 = 0x0; +const RISCV_OP_ADD_SUB: u8 = 0x20; +const RISCV_OP_SR_SRL: u8 = 0x0; +const RISCV_OP_SR_SRA: u8 = 0x20; + +const RISCV_SYSTEM: u8 = 0x73; + +const RISCV_OPIW_ADDIW: u8 = 0x0; +const RISCV_OPIW_SLLIW: u8 = 0x1; +const RISCV_OPIW_SRW: u8 = 0x5; +const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; +const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; + +const RISCV_OPW_ADDSUBW: u8 = 0x0; +const RISCV_OPW_SLLW: u8 = 0x1; +const RISCV_OPW_SRW: u8 = 0x5; +const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; +const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; +const RISCV_OPW_SRW_SRLW: u8 = 0x0; +const RISCV_OPW_SRW_SRAW: u8 = 0x20; + +const RISCV_SYSTEM_ENV: u8 = 0x0; +const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; +const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; +const RISCV_SYSTEM_CSRRS: u8 = 0x2; +const RISCV_SYSTEM_CSRRW: u8 = 0x1; +const RISCV_SYSTEM_CSRRC: u8 = 0x3; +const RISCV_SYSTEM_CSRRWI: u8 = 0x5; +const RISCV_SYSTEM_CSRRSI: u8 = 0x6; +const RISCV_SYSTEM_CSRRCI: u8 = 0x7; + +const RISCV_FLW: u8 = 0x07; +const RISCV_FSW: u8 = 0x27; +const RISCV_FMADD: u8 = 0x43; +const RISCV_FMSUB: u8 = 0x47; +const RISCV_FNMSUB: u8 = 0x4b; +const RISCV_FNMADD: u8 = 0x4f; +const RISCV_FP: u8 = 0x53; + +const RISCV_FP_ADD: u8 = 0x0; +const RISCV_FP_SUB: u8 = 0x4; +const RISCV_FP_MUL: u8 = 0x8; +const RISCV_FP_DIV: u8 = 0xc; +const RISCV_FP_SQRT: u8 = 0x2c; +const RISCV_FP_FSGN: u8 = 0x10; +const RISCV_FP_MINMAX: u8 = 0x14; +const RISCV_FP_FCVTW: u8 = 0x60; +const RISCV_FP_FMVXFCLASS: u8 = 0x70; +const RISCV_FP_FCMP: u8 = 0x50; +const RISCV_FP_FEQS: u8 = 0x53; +const RISCV_FP_FCVTS: u8 = 0x68; +const RISCV_FP_FCVTDS: u8 = 0x21; + +const RISCV_FP_FSGN_J: u8 = 0x0; +const RISCV_FP_FSGN_JN: u8 = 0x1; +const RISCV_FP_FSGN_JX: u8 = 0x2; + +const RISCV_FP_MINMAX_MIN: u8 = 0x0; +const RISCV_FP_MINMAX_MAX: u8 = 0x1; + +const RISCV_FP_FCVTW_W: u8 = 0x0; +const RISCV_FP_FCVTW_WU: u8 = 0x1; + +const RISCV_FP_FCVTS_W: u8 = 0x0; +const RISCV_FP_FCVTS_WU: u8 = 0x1; + +const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; +const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; + +const RISCV_FP_FCMP_FEQ: u8 = 2; +const RISCV_FP_FCMP_FLT: u8 = 1; +const RISCV_FP_FCMP_FLE: u8 = 0; + +const RISCV_FP_FMVW: u8 = 0x78; + + +const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; +const names_opi: [&str; 8] = ["addi", "slli", "slti", "cmpltuii", "xori", "slri", "ori", "andi"]; +const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; +const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; +const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; +const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; +const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; +const names_opiw: [&str; 8] = ["addwi", "sllwi", "", "", "", "sri", "", ""]; + + + +pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 + + match ins.opcode { + RISCV_OP => { + let name: &str; + if ins.funct7 == 1 { // Use mul array + name = names_mul[ins.funct3 as usize] + } else { + name = names_op[ins.funct3 as usize]; + } + format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string()) + }, + RISCV_OPI => { + // SHAMT OR IMM + if ins.funct3 == RISCV_OPI_SRI { + if ins.funct7 == RISCV_OPI_SRI_SRLI { + format!("slrii x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + } else { + format!("srai x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + } + } else if ins.funct3 == RISCV_OPI_SLLI { + format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + } else { + format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) + } + }, + RISCV_LUI => { + format!("lui x{}, {}", ins.rd.to_string(), ins.imm31_12.to_string()) //TODO Value is supposed to be in hex + }, + RISCV_AUIPC => { + format!("auipc x{}, {}", ins.rd.to_string(), ins.imm31_12.to_string()) // TODO Value is supposed to be in hex + }, + RISCV_JAL => { + if ins.rd == 0 { + format!("j {}", ins.imm31_12.to_string()) + } else { + format!("jal x{}, {}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed).to_string()) // TODO Value is supposed to be in hex + } + }, + RISCV_JALR => { + if ins.rd == 0 { + if ins.rs1 == 1 { + "ret".to_string() + } else { + format!("jr {}", ins.imm31_12.to_string()) // TODO Value is supposed to be in hex + } + } else { + format!("jalr {}, (r{})", ins.imm12_I_signed.to_string(), ins.rs1.to_string()) + } + }, + RISCV_BR => { + format!("{} r{} x{} {}", names_br[ins.funct3 as usize].to_string(), ins.rs1.to_string(), ins.rs2.to_string(), ins.imm13_signed.to_string()) + }, + RISCV_LD => { + format!("{} x{}, {}(x{})", names_ld[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.imm12_I_signed.to_string(), ins.rs1.to_string()) + }, + RISCV_ST => { + format!("{} x{}, {}(x{})", names_st[ins.funct3 as usize].to_string(), ins.rs2.to_string(), ins.imm12_S_signed.to_string(), ins.rs1.to_string()) + }, + RISCV_OPIW => { + if ins.funct3 == RISCV_OPIW_SRW { + if ins.funct7 == RISCV_OPIW_SRW_SRLIW { + format!("srlwi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } else { + format!("srawi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } + } else if ins.funct3 == RISCV_OPIW_SLLIW { + format!("{} x{}, x{}, x{}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } else { + format!("{} x{}, x{}, x{}", names_opiw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) + } + }, + RISCV_OPW => { + if ins.funct7 == 1 { + format!("{}w x{}, x{}, x{}", names_mul[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } else { + if ins.funct3 == RISCV_OP_ADD { + if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { + format!("addw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } else { + format!("subw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } + } else if ins.funct3 == RISCV_OPW_SRW { + if ins.funct7 == RISCV_OPW_SRW_SRLW { + format!("srlw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } else { + format!("sraw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } + } else { + format!("{} x{}, x{}, x{}", names_opw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + } + } + }, + RISCV_SYSTEM => { + "ecall".to_string() + }, + _ => "Unknown".to_string() // Error + } + +} \ No newline at end of file From f67bd4a5a8ed680b37f1716d0a5fda3fcb0b5c05 Mon Sep 17 00:00:00 2001 From: Keizaal Date: Wed, 26 Oct 2022 14:59:37 +0200 Subject: [PATCH 004/128] imported decode.rs in print.rs to use structure Instruction --- src/print.rs | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) diff --git a/src/print.rs b/src/print.rs index 13a54d0..65ef08f 100644 --- a/src/print.rs +++ b/src/print.rs @@ -1,30 +1,4 @@ -pub struct Instruction { - value : u64, - - opcode : u8, - rs1 : u8, - rs2 : u8, - rs3 : u8, - rd : u8, - funct7 : u8, - funct7_smaller : u8, - funct3 : u8, - shamt : u8, - - imm12_I : u16, - imm12_S : u16, - - imm12_I_signed : i16, - imm12_S_signed : i16, - imm13 : i16, - imm13_signed : i16, - - imm31_12 : u32, - imm21_1 : u32, - - imm31_12_signed : i32, - imm21_1_signed : i32, -} +mod decode.rs const RISCV_LUI: u8 = 0x37; const RISCV_AUIPC: u8 = 0x17; From 7f9fb76513d3c8b2ac77f6d073e2a98e726e1529 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 26 Oct 2022 15:06:37 +0200 Subject: [PATCH 005/128] import Instruction and use print in main --- src/main.rs | 3 ++- src/print.rs | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main.rs b/src/main.rs index 16cda16..aefc218 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,6 +1,7 @@ mod decode; +mod print; fn main() { let instr = decode::decode(98); - println!("Hello, world! opcode : {}", instr.opcode); + println!("{}", print::print(instr, 0)); } diff --git a/src/print.rs b/src/print.rs index 65ef08f..c2e2e47 100644 --- a/src/print.rs +++ b/src/print.rs @@ -1,4 +1,4 @@ -mod decode.rs +use crate::decode::Instruction; const RISCV_LUI: u8 = 0x37; const RISCV_AUIPC: u8 = 0x17; From 673c2c8d20a279d84709e5e080ad1446bda57c28 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 26 Oct 2022 15:10:21 +0200 Subject: [PATCH 006/128] Added hex conversion --- src/print.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/print.rs b/src/print.rs index c2e2e47..28bcb25 100644 --- a/src/print.rs +++ b/src/print.rs @@ -166,16 +166,16 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui x{}, {}", ins.rd.to_string(), ins.imm31_12.to_string()) //TODO Value is supposed to be in hex + format!("lui x{}, {:X}", ins.rd.to_string(), ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc x{}, {}", ins.rd.to_string(), ins.imm31_12.to_string()) // TODO Value is supposed to be in hex + format!("auipc x{}, {:X}", ins.rd.to_string(), ins.imm31_12) }, RISCV_JAL => { if ins.rd == 0 { format!("j {}", ins.imm31_12.to_string()) } else { - format!("jal x{}, {}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed).to_string()) // TODO Value is supposed to be in hex + format!("jal x{}, {:X}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed)) } }, RISCV_JALR => { @@ -183,7 +183,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 if ins.rs1 == 1 { "ret".to_string() } else { - format!("jr {}", ins.imm31_12.to_string()) // TODO Value is supposed to be in hex + format!("jr {:X}", ins.imm31_12) } } else { format!("jalr {}, (r{})", ins.imm12_I_signed.to_string(), ins.rs1.to_string()) From 7a89d06f36da2b91d49214ea18fc69ec4b3459a1 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 9 Nov 2022 14:37:19 +0100 Subject: [PATCH 007/128] RISCV_OP fixed --- src/print.rs | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/print.rs b/src/print.rs index 28bcb25..2f4d185 100644 --- a/src/print.rs +++ b/src/print.rs @@ -147,7 +147,23 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 if ins.funct7 == 1 { // Use mul array name = names_mul[ins.funct3 as usize] } else { - name = names_op[ins.funct3 as usize]; + if ins.funct3 == RISCV_OP_ADD { + // Add or Sub + if ins.funct7 == RISCV_OP_ADD_ADD { + name = "add"; + } else { + name = "sub"; + } + } else if ins.funct3 == RISCV_OP_SR { + // Srl or Sra + if ins.funct7 == RISCV_OP_SR_SRL { + name = "srl"; + } else { + name = "sra"; + } + } else { + name = names_op[ins.funct3 as usize]; + } } format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string()) }, From 756410e5b4c12fcc570bfa37ef92607ac26b320b Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 9 Nov 2022 15:06:22 +0100 Subject: [PATCH 008/128] Added some tests --- src/print.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/print.rs b/src/print.rs index 2f4d185..d4651ba 100644 --- a/src/print.rs +++ b/src/print.rs @@ -1,3 +1,5 @@ +#![allow(dead_code)] +#![allow(unused_variables)] use crate::decode::Instruction; const RISCV_LUI: u8 = 0x37; @@ -254,4 +256,26 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 _ => "Unknown".to_string() // Error } +} + + +#[cfg(test)] +mod Test { + use crate::{print, decode}; + + #[test] + fn test1() { + let sub = decode::decode(0b01000001000010001000111000110011); + let add = decode::decode(0b00000001000010001000111000110011); + let xor = decode::decode(0b00000001000010001100111000110011); + let slr = decode::decode(0b00000001000010001101111000110011); + let sra = decode::decode(0b01000001000010001101111000110011); + + assert_eq!("sub r28, r17, r16", print::print(sub, 0)); + assert_eq!("xor r28, r17, r16", print::print(xor, 0)); + assert_eq!("srl r28, r17, r16", print::print(slr, 0)); + assert_eq!("sra r28, r17, r16", print::print(sra, 0)); + assert_eq!("add r28, r17, r16", print::print(add, 0)); + + } } \ No newline at end of file From b685c198b3fdcd61271f0e91d80b99c64709b0ad Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 9 Nov 2022 15:10:03 +0100 Subject: [PATCH 009/128] change Instruction to 32bits --- src/decode.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index 80ac041..43e04fa 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -1,5 +1,5 @@ pub struct Instruction { - pub value : u64, + pub value : u32, pub opcode : u8, pub rs1 : u8, @@ -26,7 +26,7 @@ pub struct Instruction { pub imm21_1_signed : i32, } -pub fn decode(val : u64) -> Instruction { +pub fn decode(val : u32) -> Instruction { let value = val; From 3b17ffcaa6458c7382f06a9d5bd785906328e584 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 9 Nov 2022 15:54:01 +0100 Subject: [PATCH 010/128] add addi print test --- src/decode.rs | 3 +++ src/print.rs | 21 ++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index 80ac041..7aa2d87 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -1,3 +1,5 @@ +#[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules) +#[derive(Debug)] pub struct Instruction { pub value : u64, @@ -26,6 +28,7 @@ pub struct Instruction { pub imm21_1_signed : i32, } +#[allow(non_snake_case)] pub fn decode(val : u64) -> Instruction { let value = val; diff --git a/src/print.rs b/src/print.rs index d4651ba..2435951 100644 --- a/src/print.rs +++ b/src/print.rs @@ -260,16 +260,16 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] -mod Test { +mod test { use crate::{print, decode}; #[test] - fn test1() { - let sub = decode::decode(0b01000001000010001000111000110011); - let add = decode::decode(0b00000001000010001000111000110011); - let xor = decode::decode(0b00000001000010001100111000110011); - let slr = decode::decode(0b00000001000010001101111000110011); - let sra = decode::decode(0b01000001000010001101111000110011); + fn test_op() { + let sub = decode::decode(0b0100000_10000_10001_000_11100_0110011); + let add = decode::decode(0b0000000_10000_10001_000_11100_0110011); + let xor = decode::decode(0b0000000_10000_10001_100_11100_0110011); + let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); + let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); assert_eq!("sub r28, r17, r16", print::print(sub, 0)); assert_eq!("xor r28, r17, r16", print::print(xor, 0)); @@ -278,4 +278,11 @@ mod Test { assert_eq!("add r28, r17, r16", print::print(add, 0)); } + + #[test] + fn test_opi() { + let addi = decode::decode(0b0000000000_10001_000_11100_0010011); + assert_eq!("addi x28, x17, 0", print::print(addi, 0)); + } + } \ No newline at end of file From c377929ce10739d66501a370f01934db8dd3aa7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 9 Nov 2022 15:59:05 +0100 Subject: [PATCH 011/128] Creating machine.rs file --- src/machine.rs | 27 +++++++++++++++++++++++++++ src/main.rs | 1 + 2 files changed, 28 insertions(+) create mode 100644 src/machine.rs diff --git a/src/machine.rs b/src/machine.rs new file mode 100644 index 0000000..5845ae3 --- /dev/null +++ b/src/machine.rs @@ -0,0 +1,27 @@ +use crate::decode::*; + + +pub struct Machine { + pub _pc : u32, + pub _int_reg : [u32 ; 32], + pub _instructions : [u32 ; 100] +} + + +impl Machine { + + fn _init_machine() -> Machine { + + Machine { + _pc : 0, + _instructions : [0 ; 100], + _int_reg : [0 ; 32] + } + } +} + +#[cfg(test)] + mod test { + use crate::{_init_machine}; + + } diff --git a/src/main.rs b/src/main.rs index aefc218..346a5b8 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,5 +1,6 @@ mod decode; mod print; +mod machine; fn main() { let instr = decode::decode(98); From c920f71c45cb9d910e47b2fae2e30e480d394046 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 9 Nov 2022 16:08:51 +0100 Subject: [PATCH 012/128] tests lui and ld --- src/print.rs | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/src/print.rs b/src/print.rs index 2435951..6aaa052 100644 --- a/src/print.rs +++ b/src/print.rs @@ -184,7 +184,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui x{}, {:X}", ins.rd.to_string(), ins.imm31_12) + format!("lui x{}, 0x{:X}", ins.rd.to_string(), ins.imm31_12) }, RISCV_AUIPC => { format!("auipc x{}, {:X}", ins.rd.to_string(), ins.imm31_12) @@ -285,4 +285,30 @@ mod test { assert_eq!("addi x28, x17, 0", print::print(addi, 0)); } + #[test] + fn test_lui() { + let lui = decode::decode(0b01110001000011111000_11100_0110111); + assert_eq!("lui x28, 0x710F8000", print::print(lui, 0)); + } + + #[test] + fn test_ld() { + // imm rs1 f3 rd opcode + let lb = decode::decode(0b010111110000_10001_000_11100_0000011); + let lh = decode::decode(0b010111110000_10001_001_11100_0000011); + let lw = decode::decode(0b010111110000_10001_010_11100_0000011); + let lbu = decode::decode(0b010111110000_10001_100_11100_0000011); + let lhu = decode::decode(0b010111110000_10001_101_11100_0000011); + let ld = decode::decode(0b010111110000_10001_011_11100_0000011); + let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); + // TODO: imm négatif produit une erreur + assert_eq!("lb x28, 1520(x17)", print::print(lb, 0)); + assert_eq!("lh x28, 1520(x17)", print::print(lh, 0)); + assert_eq!("lw x28, 1520(x17)", print::print(lw, 0)); + assert_eq!("lbu x28, 1520(x17)", print::print(lbu, 0)); + assert_eq!("lhu x28, 1520(x17)", print::print(lhu, 0)); + assert_eq!("ld x28, 1520(x17)", print::print(ld, 0)); + assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0)); + } + } \ No newline at end of file From 4e44c5a9ecb5826b0d0db13e0ec3664a37fcb876 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 9 Nov 2022 16:38:50 +0100 Subject: [PATCH 013/128] Add test for opi, fix func3 sltiu --- src/print.rs | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/print.rs b/src/print.rs index 2435951..89165cb 100644 --- a/src/print.rs +++ b/src/print.rs @@ -131,7 +131,7 @@ const RISCV_FP_FMVW: u8 = 0x78; const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; -const names_opi: [&str; 8] = ["addi", "slli", "slti", "cmpltuii", "xori", "slri", "ori", "andi"]; +const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; @@ -261,6 +261,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] mod test { + use crate::{print, decode}; #[test] @@ -282,7 +283,17 @@ mod test { #[test] fn test_opi() { let addi = decode::decode(0b0000000000_10001_000_11100_0010011); + let slli = decode::decode(0b0000000000_10001_001_11100_0010011); + let slti = decode::decode(0b0000000000_10001_010_11100_0010011); + let sltiu = decode::decode(0b0000000000_10001_011_11100_0010011); + let xori = decode::decode(0b_0000000000010001_100_11100_0010011); + let ori = decode::decode(0b00000000000_10001_110_11100_0010011); assert_eq!("addi x28, x17, 0", print::print(addi, 0)); + assert_eq!("slli x28, x17, 0", print::print(slli, 0)); + assert_eq!("slti x28, x17, 0", print::print(slti, 0)); + assert_eq!("sltiu x28, x17, 0", print::print(sltiu, 0)); + assert_eq!("xori x28, x17, 0", print::print(xori, 0)); + assert_eq!("ori x28, x17, 0", print::print(ori, 0)); } } \ No newline at end of file From 2a708ce335bd2f2c77e6a8b34216f3c1858ab3d3 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 9 Nov 2022 16:45:00 +0100 Subject: [PATCH 014/128] Fix machine.rs --- src/machine.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine.rs b/src/machine.rs index 5845ae3..1ac9c62 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -22,6 +22,6 @@ impl Machine { #[cfg(test)] mod test { - use crate::{_init_machine}; + use super::Machine; } From a341493526ff9d4a23b82e46d5c0e2e23ad5c98f Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 9 Nov 2022 16:47:26 +0100 Subject: [PATCH 015/128] first instruction in oneInstruction() --- src/machine.rs | 37 ++++++++++++++++++++++++++++--------- src/main.rs | 4 ++++ 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 5845ae3..7cf6fe8 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,23 +1,42 @@ -use crate::decode::*; +#[warn(unused_parens)] +use crate::decode::*; +use crate::print::*; pub struct Machine { - pub _pc : u32, - pub _int_reg : [u32 ; 32], - pub _instructions : [u32 ; 100] + pub pc : u32, + pub int_reg : [u32 ; 32], + pub instructions : [u32 ; 100] } impl Machine { - - fn _init_machine() -> Machine { + + pub fn _init_machine() -> Machine { Machine { - _pc : 0, - _instructions : [0 ; 100], - _int_reg : [0 ; 32] + pc : 0, + instructions : [0 ; 100], + int_reg : [0 ; 32] } } + + pub fn oneInstruction(mut machine : Machine) -> Machine { + if (machine.instructions.len() <= machine.pc as usize) { + println!("ERROR : number max of instructions rushed"); + return machine; + } + let inst : Instruction = decode(machine.instructions[machine.pc as usize]); + machine.pc += 1; + match (inst.opcode) { + RISCV_LUI => { + machine.int_reg[inst.rd as usize] = inst.imm31_12; + }, + } + + + machine + } } #[cfg(test)] diff --git a/src/main.rs b/src/main.rs index 346a5b8..9eb5d76 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,4 +5,8 @@ mod machine; fn main() { let instr = decode::decode(98); println!("{}", print::print(instr, 0)); + + let mut m = machine::Machine::_init_machine(); + m.instructions[0] = 0x37; + machine::Machine::oneInstruction(m); } From 2a3f0b3bb3affaefaef3bcb04eaa8797ba13361b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 9 Nov 2022 17:31:14 +0100 Subject: [PATCH 016/128] Fix decode to allow overflow in certains cases, add a case in test for riscv_lui where imm is negative --- src/decode.rs | 8 +++++--- src/print.rs | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index 3ef5bdb..68d0e2f 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -1,3 +1,5 @@ +use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations voulues + #[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules) #[derive(Debug)] pub struct Instruction { @@ -45,8 +47,8 @@ pub fn decode(val : u32) -> Instruction { let imm12_I = ((val >> 20) & 0xfff) as u16; let imm12_S = (((val >> 20) & 0xfe0) + ((val >> 7) & 0x1f)) as u16; - let imm12_I_signed = if imm12_I >= 2048 { imm12_I - 4096 } else { imm12_I } as i16; - let imm12_S_signed = if imm12_S >= 2048 { imm12_S - 4096 } else { imm12_S } as i16; + let imm12_I_signed = if imm12_I >= 2048 { (Wrapping(imm12_I) - Wrapping(4096)).0 } else { imm12_I } as i16; + let imm12_S_signed = if imm12_S >= 2048 { (Wrapping(imm12_S) - Wrapping(4096)).0 } else { imm12_S } as i16; let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) + ((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16; @@ -57,7 +59,7 @@ pub fn decode(val : u32) -> Instruction { let imm21_1 = ((val & 0xff000) + ((val >> 9) & 0x800) + ((val >> 20) & 0x7fe) + ((val >> 11) & 0x100000)) as u32; - let imm21_1_signed = if imm21_1 >= 1048576 { imm21_1 - 2097152 } else { imm21_1 } as i32; + let imm21_1_signed = if imm21_1 >= 1048576 { (Wrapping(imm21_1) - Wrapping(2097152)).0 } else { imm21_1 } as i32; let shamt = ((val >> 20) & 0x3f) as u8; diff --git a/src/print.rs b/src/print.rs index 3e4eb00..aac1952 100644 --- a/src/print.rs +++ b/src/print.rs @@ -299,7 +299,9 @@ mod test { #[test] fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); + let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); assert_eq!("lui x28, 0x710F8000", print::print(lui, 0)); + assert_eq!("lui x28, 0xF10F8000", print::print(lui_negatif, 0)); } #[test] From 240f029881a1c975f3b88b864ea9c640a78044bf Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 9 Nov 2022 17:35:16 +0100 Subject: [PATCH 017/128] simulate some instructions --- src/machine.rs | 30 ++++++++++++++++++++++++++++-- src/main.rs | 8 +++----- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index bc53171..71a2ed5 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,5 +1,3 @@ -#[warn(unused_parens)] - use crate::decode::*; use crate::print::*; @@ -26,12 +24,40 @@ impl Machine { println!("ERROR : number max of instructions rushed"); return machine; } + let inst : Instruction = decode(machine.instructions[machine.pc as usize]); machine.pc += 1; + match (inst.opcode) { RISCV_LUI => { machine.int_reg[inst.rd as usize] = inst.imm31_12; }, + + //****************************************************************************************** + // Treatment for: OPI INSTRUCTIONS + RISCV_OPI => { + match (inst.funct3) { + RISCV_OPI_ADDI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32; + }, + RISCV_OPI_SLTI => { + machine.int_reg[inst.rd as usize] = + if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 }; + }, + RISCV_OPI_XORI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32; + }, + RISCV_OPI_ORI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32; + }, + RISCV_OPI_ANDI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32; + }, + RISCV_OPI_SLLI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + } + } + }, } diff --git a/src/main.rs b/src/main.rs index 9eb5d76..f21a6d7 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,12 +1,10 @@ mod decode; mod print; mod machine; +use machine::Machine; fn main() { - let instr = decode::decode(98); - println!("{}", print::print(instr, 0)); - - let mut m = machine::Machine::_init_machine(); + let mut m = Machine::_init_machine(); m.instructions[0] = 0x37; - machine::Machine::oneInstruction(m); + Machine::oneInstruction(m); } From c1e188df22e446805cf143cc27a99b72a65e4f9e Mon Sep 17 00:00:00 2001 From: AmauryBrodu <60550980+AmauryBrodu@users.noreply.github.com> Date: Thu, 10 Nov 2022 00:08:06 +0100 Subject: [PATCH 018/128] ajout de l'instruction andi --- src/print.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/print.rs b/src/print.rs index aac1952..750dc9b 100644 --- a/src/print.rs +++ b/src/print.rs @@ -288,6 +288,8 @@ mod test { let sltiu = decode::decode(0b0000000000_10001_011_11100_0010011); let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011); + let andi = decode::decode(0b000000000000_10001_111_11100_0010011); + assert_eq!("andi x28, x17, 0", print::print(andi, 0)); assert_eq!("addi x28, x17, 0", print::print(addi, 0)); assert_eq!("slli x28, x17, 0", print::print(slli, 0)); assert_eq!("slti x28, x17, 0", print::print(slti, 0)); @@ -324,4 +326,6 @@ mod test { assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0)); } + + } \ No newline at end of file From 5a5afda8beeaad009b1caf5d24e078ac40b02c3f Mon Sep 17 00:00:00 2001 From: AmauryBrodu <60550980+AmauryBrodu@users.noreply.github.com> Date: Thu, 10 Nov 2022 00:16:21 +0100 Subject: [PATCH 019/128] ajout des test des instructions opw --- src/print.rs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/print.rs b/src/print.rs index 750dc9b..9b5bede 100644 --- a/src/print.rs +++ b/src/print.rs @@ -326,6 +326,18 @@ mod test { assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0)); } + #[test] + fn test_opw() { + let addw: decode::Instruction = decode::decode(0b0000000_10000_10001_000_11100_0111011); + let sllw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0111011); + let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); + let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); + + assert_eq!("addw x28, x17, x16", print::print(addw, 0)); + assert_eq!("sllw x28, x17, x16", print::print(sllw, 0)); + assert_eq!("srlw x28, x17, x16", print::print(srlw, 0)); + assert_eq!("sraw x28, x17, x16", print::print(sraw, 0)); + } } \ No newline at end of file From 3b9a23948a7c86b703ab7dfc84da23d827d6139c Mon Sep 17 00:00:00 2001 From: AmauryBrodu <60550980+AmauryBrodu@users.noreply.github.com> Date: Thu, 10 Nov 2022 00:39:11 +0100 Subject: [PATCH 020/128] add of the test function for opwi instructions --- src/print.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/print.rs b/src/print.rs index 9b5bede..e51f0d2 100644 --- a/src/print.rs +++ b/src/print.rs @@ -339,5 +339,15 @@ mod test { assert_eq!("sraw x28, x17, x16", print::print(sraw, 0)); } + #[test] + fn test_opwi() { + let addwi: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); + let sllwi: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); + let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); + assert_eq!("addwi x28, x17, x0", print::print(addwi, 0)); + assert_eq!("slli x28, x17, x16", print::print(sllwi, 0)); + assert_eq!("srai x28, x17, 17", print::print(srai, 0)); + + } } \ No newline at end of file From c7bf66f210ea2ce6112b813dea037662c7237e90 Mon Sep 17 00:00:00 2001 From: AmauryBrodu <60550980+AmauryBrodu@users.noreply.github.com> Date: Thu, 10 Nov 2022 00:47:32 +0100 Subject: [PATCH 021/128] add of the test function for br instructions --- src/print.rs | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/print.rs b/src/print.rs index e51f0d2..da9f92f 100644 --- a/src/print.rs +++ b/src/print.rs @@ -350,4 +350,20 @@ mod test { } + #[test] + fn test_br() { + let beq: decode::Instruction = decode::decode(0b0000000_10000_10001_000_00000_1100011); + let bne: decode::Instruction = decode::decode(0b0000000_10000_10001_001_00000_1100011); + let blt: decode::Instruction = decode::decode(0b0000000_10000_10001_100_00000_1100011); + let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); + let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); + let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); + assert_eq!("blt r17 x16 0", print::print(blt, 0)); + assert_eq!("bge r17 x16 0", print::print(bge, 0)); + assert_eq!("bltu r17 x16 0", print::print(bltu, 0)); + assert_eq!("bgeu r17 x16 0", print::print(bgeu, 0)); + assert_eq!("bne r17 x16 0", print::print(bne, 0)); + assert_eq!("beq r17 x16 0", print::print(beq, 0)); + } + } \ No newline at end of file From f9dba1ac117be2bf8269e3560e9e021943c0c257 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Tue, 15 Nov 2022 21:21:24 +0100 Subject: [PATCH 022/128] machine : Instruction type RISCV_OP --- src/machine.rs | 75 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 70 insertions(+), 5 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 71a2ed5..34bc8df 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,10 +1,17 @@ use crate::decode::*; use crate::print::*; +//doit disparaitre +const MEM_SIZE : usize= 4096; + + pub struct Machine { pub pc : u32, pub int_reg : [u32 ; 32], - pub instructions : [u32 ; 100] + pub instructions : [u32 ; 100], + pub mainMemory : [u8 ; MEM_SIZE] + // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; + //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -15,20 +22,26 @@ impl Machine { Machine { pc : 0, instructions : [0 ; 100], - int_reg : [0 ; 32] + int_reg : [0 ; 32], + mainMemory : [0 ; MEM_SIZE] } } pub fn oneInstruction(mut machine : Machine) -> Machine { + + let mut unsignedReg1 : u64 = 0; + let mut unsignedReg2 : u64 = 0; + if (machine.instructions.len() <= machine.pc as usize) { println!("ERROR : number max of instructions rushed"); return machine; } let inst : Instruction = decode(machine.instructions[machine.pc as usize]); - machine.pc += 1; + + machine.pc += 4; - match (inst.opcode) { + match inst.opcode { RISCV_LUI => { machine.int_reg[inst.rd as usize] = inst.imm31_12; }, @@ -36,7 +49,7 @@ impl Machine { //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { - match (inst.funct3) { + match inst.funct3 { RISCV_OPI_ADDI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32; }, @@ -58,6 +71,58 @@ impl Machine { } } }, + + RISCV_JAL => { + machine.int_reg[inst.rd as usize] = machine.pc; + machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u32); + }, + + RISCV_OP => { + match inst.funct3 { + RISCV_OP_ADD => { + // RISCV_OP_ADD_ADD inaccessible + /*if (inst.funct7 == RISCV_OP_ADD_ADD) { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; + //} + }, + RISCV_OP_SLL => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); + }, + RISCV_OP_SLT => { + if(machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize]){ + machine.int_reg[inst.rd as usize] = 1; + } else { + machine.int_reg[inst.rd as usize] = 0; + } + }, + RISCV_OP_SLTU => { + unsignedReg1 = machine.int_reg[inst.rs1 as usize] as u64; + unsignedReg2 = machine.int_reg[inst.rs2 as usize] as u64; + if(unsignedReg1 < unsignedReg2){ + machine.int_reg[inst.rd as usize] = 1; + } else { + machine.int_reg[inst.rd as usize] = 0; + } + }, + RISCV_OP_XOR => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; + }, + RISCV_OP_SR => { + // RISCV_OP_SR_SRL inaccessible + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); + }, + RISCV_OP_OR => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; + }, + RISCV_OP_AND => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; + }, + _ => { + println!("RISCV_OP undefined case\n"); + } + } + }, } From 9a233f3c12b63d5ed5e38647989b4d547365ec30 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 16 Nov 2022 15:48:46 +0100 Subject: [PATCH 023/128] Remove ~60 warnings --- src/machine.rs | 26 +++--- src/main.rs | 2 +- src/print.rs | 215 +++++++++++++++++++++++++------------------------ 3 files changed, 123 insertions(+), 120 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 34bc8df..22a6b7a 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,7 +1,7 @@ use crate::decode::*; use crate::print::*; -//doit disparaitre +// doit disparaitre const MEM_SIZE : usize= 4096; @@ -9,7 +9,7 @@ pub struct Machine { pub pc : u32, pub int_reg : [u32 ; 32], pub instructions : [u32 ; 100], - pub mainMemory : [u8 ; MEM_SIZE] + pub main_memory : [u8 ; MEM_SIZE] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -23,16 +23,16 @@ impl Machine { pc : 0, instructions : [0 ; 100], int_reg : [0 ; 32], - mainMemory : [0 ; MEM_SIZE] + main_memory : [0 ; MEM_SIZE] } } - pub fn oneInstruction(mut machine : Machine) -> Machine { + pub fn one_instruction(mut machine : Machine) -> Machine { - let mut unsignedReg1 : u64 = 0; - let mut unsignedReg2 : u64 = 0; + let mut unsigned_reg1 : u64 = 0; + let mut unsigned_reg2 : u64 = 0; - if (machine.instructions.len() <= machine.pc as usize) { + if machine.instructions.len() <= machine.pc as usize { println!("ERROR : number max of instructions rushed"); return machine; } @@ -69,6 +69,7 @@ impl Machine { RISCV_OPI_SLLI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; } + _ => { println!("{} inconnu", inst.funct3); } } }, @@ -90,16 +91,16 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); }, RISCV_OP_SLT => { - if(machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize]){ + if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { machine.int_reg[inst.rd as usize] = 1; } else { machine.int_reg[inst.rd as usize] = 0; } }, RISCV_OP_SLTU => { - unsignedReg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsignedReg2 = machine.int_reg[inst.rs2 as usize] as u64; - if(unsignedReg1 < unsignedReg2){ + unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; + unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + if unsigned_reg1 < unsigned_reg2 { machine.int_reg[inst.rd as usize] = 1; } else { machine.int_reg[inst.rd as usize] = 0; @@ -122,7 +123,8 @@ impl Machine { println!("RISCV_OP undefined case\n"); } } - }, + } + _ => { println!("{} opcode non géré", inst.opcode)}, } diff --git a/src/main.rs b/src/main.rs index f21a6d7..5f265bb 100644 --- a/src/main.rs +++ b/src/main.rs @@ -6,5 +6,5 @@ use machine::Machine; fn main() { let mut m = Machine::_init_machine(); m.instructions[0] = 0x37; - Machine::oneInstruction(m); + Machine::one_instruction(m); } diff --git a/src/print.rs b/src/print.rs index da9f92f..4aa70b0 100644 --- a/src/print.rs +++ b/src/print.rs @@ -2,132 +2,133 @@ #![allow(unused_variables)] use crate::decode::Instruction; -const RISCV_LUI: u8 = 0x37; -const RISCV_AUIPC: u8 = 0x17; -const RISCV_JAL: u8 = 0x6f; -const RISCV_JALR: u8 = 0x67; -const RISCV_BR: u8 = 0x63; -const RISCV_LD: u8 = 0x3; -const RISCV_ST: u8 = 0x23; -const RISCV_OPI: u8 = 0x13; -const RISCV_OP: u8 = 0x33; -const RISCV_OPIW: u8 = 0x1b; -const RISCV_OPW: u8 = 0x3b; + +pub const RISCV_LUI: u8 = 0x37; +pub const RISCV_AUIPC: u8 = 0x17; +pub const RISCV_JAL: u8 = 0x6f; +pub const RISCV_JALR: u8 = 0x67; +pub const RISCV_BR: u8 = 0x63; +pub const RISCV_LD: u8 = 0x3; +pub const RISCV_ST: u8 = 0x23; +pub const RISCV_OPI: u8 = 0x13; +pub const RISCV_OP: u8 = 0x33; +pub const RISCV_OPIW: u8 = 0x1b; +pub const RISCV_OPW: u8 = 0x3b; -const RISCV_BR_BEQ: u8 = 0x0; -const RISCV_BR_BNE: u8 = 0x1; -const RISCV_BR_BLT: u8 = 0x4; -const RISCV_BR_BGE: u8 = 0x5; -const RISCV_BR_BLTU: u8 = 0x6; -const RISCV_BR_BGEU: u8 = 0x7; +pub const RISCV_BR_BEQ: u8 = 0x0; +pub const RISCV_BR_BNE: u8 = 0x1; +pub const RISCV_BR_BLT: u8 = 0x4; +pub const RISCV_BR_BGE: u8 = 0x5; +pub const RISCV_BR_BLTU: u8 = 0x6; +pub const RISCV_BR_BGEU: u8 = 0x7; -const RISCV_LD_LB: u8 = 0x0; -const RISCV_LD_LH: u8 = 0x1; -const RISCV_LD_LW: u8 = 0x2; -const RISCV_LD_LD: u8 = 0x3; -const RISCV_LD_LBU: u8 = 0x4; -const RISCV_LD_LHU: u8 = 0x5; -const RISCV_LD_LWU: u8 = 0x6; +pub const RISCV_LD_LB: u8 = 0x0; +pub const RISCV_LD_LH: u8 = 0x1; +pub const RISCV_LD_LW: u8 = 0x2; +pub const RISCV_LD_LD: u8 = 0x3; +pub const RISCV_LD_LBU: u8 = 0x4; +pub const RISCV_LD_LHU: u8 = 0x5; +pub const RISCV_LD_LWU: u8 = 0x6; -const RISCV_ST_STB: u8 = 0x0; -const RISCV_ST_STH: u8 = 0x1; -const RISCV_ST_STW: u8 = 0x2; -const RISCV_ST_STD: u8 = 0x3; +pub const RISCV_ST_STH: u8 = 0x1; +pub const RISCV_ST_STW: u8 = 0x2; +pub const RISCV_ST_STB: u8 = 0x0; +pub const RISCV_ST_STD: u8 = 0x3; -const RISCV_OPI_ADDI: u8 = 0x0; -const RISCV_OPI_SLTI: u8 = 0x2; -const RISCV_OPI_SLTIU: u8 = 0x3; -const RISCV_OPI_XORI: u8 = 0x4; -const RISCV_OPI_ORI: u8 = 0x6; -const RISCV_OPI_ANDI: u8 = 0x7; -const RISCV_OPI_SLLI: u8 = 0x1; -const RISCV_OPI_SRI: u8 = 0x5; -const RISCV_OPI_SRI_SRAI: u8 = 0x20; -const RISCV_OPI_SRI_SRLI: u8 = 0x0; +pub const RISCV_OPI_ADDI: u8 = 0x0; +pub const RISCV_OPI_SLTI: u8 = 0x2; +pub const RISCV_OPI_SLTIU: u8 = 0x3; +pub const RISCV_OPI_XORI: u8 = 0x4; +pub const RISCV_OPI_ORI: u8 = 0x6; +pub const RISCV_OPI_ANDI: u8 = 0x7; +pub const RISCV_OPI_SLLI: u8 = 0x1; +pub const RISCV_OPI_SRI: u8 = 0x5; +pub const RISCV_OPI_SRI_SRAI: u8 = 0x20; +pub const RISCV_OPI_SRI_SRLI: u8 = 0x0; -const RISCV_OP_ADD: u8 = 0x0; -const RISCV_OP_SLL: u8 = 0x1; -const RISCV_OP_SLT: u8 = 0x2; -const RISCV_OP_SLTU: u8 = 0x3; -const RISCV_OP_XOR: u8 = 0x4; -const RISCV_OP_SR: u8 = 0x5; -const RISCV_OP_OR: u8 = 0x6; -const RISCV_OP_AND: u8 = 0x7; -const RISCV_OP_ADD_ADD: u8 = 0x0; -const RISCV_OP_ADD_SUB: u8 = 0x20; -const RISCV_OP_SR_SRL: u8 = 0x0; -const RISCV_OP_SR_SRA: u8 = 0x20; +pub const RISCV_OP_ADD: u8 = 0x0; +pub const RISCV_OP_SLL: u8 = 0x1; +pub const RISCV_OP_SLT: u8 = 0x2; +pub const RISCV_OP_SLTU: u8 = 0x3; +pub const RISCV_OP_XOR: u8 = 0x4; +pub const RISCV_OP_SR: u8 = 0x5; +pub const RISCV_OP_OR: u8 = 0x6; +pub const RISCV_OP_AND: u8 = 0x7; +pub const RISCV_OP_ADD_ADD: u8 = 0x0; +pub const RISCV_OP_ADD_SUB: u8 = 0x20; +pub const RISCV_OP_SR_SRL: u8 = 0x0; +pub const RISCV_OP_SR_SRA: u8 = 0x20; -const RISCV_SYSTEM: u8 = 0x73; +pub const RISCV_SYSTEM: u8 = 0x73; -const RISCV_OPIW_ADDIW: u8 = 0x0; -const RISCV_OPIW_SLLIW: u8 = 0x1; -const RISCV_OPIW_SRW: u8 = 0x5; -const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; -const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; +pub const RISCV_OPIW_ADDIW: u8 = 0x0; +pub const RISCV_OPIW_SLLIW: u8 = 0x1; +pub const RISCV_OPIW_SRW: u8 = 0x5; +pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; +pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; -const RISCV_OPW_ADDSUBW: u8 = 0x0; -const RISCV_OPW_SLLW: u8 = 0x1; -const RISCV_OPW_SRW: u8 = 0x5; -const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; -const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; -const RISCV_OPW_SRW_SRLW: u8 = 0x0; -const RISCV_OPW_SRW_SRAW: u8 = 0x20; +pub const RISCV_OPW_ADDSUBW: u8 = 0x0; +pub const RISCV_OPW_SLLW: u8 = 0x1; +pub const RISCV_OPW_SRW: u8 = 0x5; +pub const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; +pub const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; +pub const RISCV_OPW_SRW_SRLW: u8 = 0x0; +pub const RISCV_OPW_SRW_SRAW: u8 = 0x20; -const RISCV_SYSTEM_ENV: u8 = 0x0; -const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; -const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; -const RISCV_SYSTEM_CSRRS: u8 = 0x2; -const RISCV_SYSTEM_CSRRW: u8 = 0x1; -const RISCV_SYSTEM_CSRRC: u8 = 0x3; -const RISCV_SYSTEM_CSRRWI: u8 = 0x5; -const RISCV_SYSTEM_CSRRSI: u8 = 0x6; -const RISCV_SYSTEM_CSRRCI: u8 = 0x7; +pub const RISCV_SYSTEM_ENV: u8 = 0x0; +pub const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; +pub const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; +pub const RISCV_SYSTEM_CSRRS: u8 = 0x2; +pub const RISCV_SYSTEM_CSRRW: u8 = 0x1; +pub const RISCV_SYSTEM_CSRRC: u8 = 0x3; +pub const RISCV_SYSTEM_CSRRWI: u8 = 0x5; +pub const RISCV_SYSTEM_CSRRSI: u8 = 0x6; +pub const RISCV_SYSTEM_CSRRCI: u8 = 0x7; -const RISCV_FLW: u8 = 0x07; -const RISCV_FSW: u8 = 0x27; -const RISCV_FMADD: u8 = 0x43; -const RISCV_FMSUB: u8 = 0x47; -const RISCV_FNMSUB: u8 = 0x4b; -const RISCV_FNMADD: u8 = 0x4f; -const RISCV_FP: u8 = 0x53; +pub const RISCV_FLW: u8 = 0x07; +pub const RISCV_FSW: u8 = 0x27; +pub const RISCV_FMADD: u8 = 0x43; +pub const RISCV_FMSUB: u8 = 0x47; +pub const RISCV_FNMSUB: u8 = 0x4b; +pub const RISCV_FNMADD: u8 = 0x4f; +pub const RISCV_FP: u8 = 0x53; -const RISCV_FP_ADD: u8 = 0x0; -const RISCV_FP_SUB: u8 = 0x4; -const RISCV_FP_MUL: u8 = 0x8; -const RISCV_FP_DIV: u8 = 0xc; -const RISCV_FP_SQRT: u8 = 0x2c; -const RISCV_FP_FSGN: u8 = 0x10; -const RISCV_FP_MINMAX: u8 = 0x14; -const RISCV_FP_FCVTW: u8 = 0x60; -const RISCV_FP_FMVXFCLASS: u8 = 0x70; -const RISCV_FP_FCMP: u8 = 0x50; -const RISCV_FP_FEQS: u8 = 0x53; -const RISCV_FP_FCVTS: u8 = 0x68; -const RISCV_FP_FCVTDS: u8 = 0x21; +pub const RISCV_FP_ADD: u8 = 0x0; +pub const RISCV_FP_SUB: u8 = 0x4; +pub const RISCV_FP_MUL: u8 = 0x8; +pub const RISCV_FP_DIV: u8 = 0xc; +pub const RISCV_FP_SQRT: u8 = 0x2c; +pub const RISCV_FP_FSGN: u8 = 0x10; +pub const RISCV_FP_MINMAX: u8 = 0x14; +pub const RISCV_FP_FCVTW: u8 = 0x60; +pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; +pub const RISCV_FP_FCMP: u8 = 0x50; +pub const RISCV_FP_FEQS: u8 = 0x53; +pub const RISCV_FP_FCVTS: u8 = 0x68; +pub const RISCV_FP_FCVTDS: u8 = 0x21; -const RISCV_FP_FSGN_J: u8 = 0x0; -const RISCV_FP_FSGN_JN: u8 = 0x1; -const RISCV_FP_FSGN_JX: u8 = 0x2; +pub const RISCV_FP_FSGN_J: u8 = 0x0; +pub const RISCV_FP_FSGN_JN: u8 = 0x1; +pub const RISCV_FP_FSGN_JX: u8 = 0x2; -const RISCV_FP_MINMAX_MIN: u8 = 0x0; -const RISCV_FP_MINMAX_MAX: u8 = 0x1; +pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; +pub const RISCV_FP_MINMAX_MAX: u8 = 0x1; -const RISCV_FP_FCVTW_W: u8 = 0x0; -const RISCV_FP_FCVTW_WU: u8 = 0x1; +pub const RISCV_FP_FCVTW_W: u8 = 0x0; +pub const RISCV_FP_FCVTW_WU: u8 = 0x1; -const RISCV_FP_FCVTS_W: u8 = 0x0; -const RISCV_FP_FCVTS_WU: u8 = 0x1; +pub const RISCV_FP_FCVTS_W: u8 = 0x0; +pub const RISCV_FP_FCVTS_WU: u8 = 0x1; -const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; -const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; +pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; +pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; -const RISCV_FP_FCMP_FEQ: u8 = 2; -const RISCV_FP_FCMP_FLT: u8 = 1; -const RISCV_FP_FCMP_FLE: u8 = 0; +pub const RISCV_FP_FCMP_FEQ: u8 = 2; +pub const RISCV_FP_FCMP_FLT: u8 = 1; +pub const RISCV_FP_FCMP_FLE: u8 = 0; -const RISCV_FP_FMVW: u8 = 0x78; +pub const RISCV_FP_FMVW: u8 = 0x78; const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; From 98f4c0b67eca10add21d2821b1bd0d9066c6c98d Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 16 Nov 2022 16:52:52 +0100 Subject: [PATCH 024/128] base --- src/machine.rs | 5 ++--- src/main.rs | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 22a6b7a..2bb70f7 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -27,14 +27,14 @@ impl Machine { } } - pub fn one_instruction(mut machine : Machine) -> Machine { + pub fn one_instruction(machine :&mut Machine) { let mut unsigned_reg1 : u64 = 0; let mut unsigned_reg2 : u64 = 0; if machine.instructions.len() <= machine.pc as usize { println!("ERROR : number max of instructions rushed"); - return machine; + return ; } let inst : Instruction = decode(machine.instructions[machine.pc as usize]); @@ -128,7 +128,6 @@ impl Machine { } - machine } } diff --git a/src/main.rs b/src/main.rs index 5f265bb..8a37ccd 100644 --- a/src/main.rs +++ b/src/main.rs @@ -6,5 +6,5 @@ use machine::Machine; fn main() { let mut m = Machine::_init_machine(); m.instructions[0] = 0x37; - Machine::one_instruction(m); + Machine::one_instruction(&mut m); } From dcd2012c6416e15d2b50a49e7a8ba36974d74ac8 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 16 Nov 2022 17:24:20 +0100 Subject: [PATCH 025/128] Register name convention --- src/print.rs | 133 ++++++++++++++++++++++++++++----------------------- 1 file changed, 73 insertions(+), 60 deletions(-) diff --git a/src/print.rs b/src/print.rs index 4aa70b0..2fc2e65 100644 --- a/src/print.rs +++ b/src/print.rs @@ -138,12 +138,25 @@ const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"] const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; -const names_opiw: [&str; 8] = ["addwi", "sllwi", "", "", "", "sri", "", ""]; +const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; +// Register name mapping +const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? +"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", +"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", +"t3", "t4", "t5", "t6"]; + +const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", +"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", +"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", +"ft8", "ft9", "ft10", "ft11"]; pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 - + let rd = ins.rd as usize; + let rs1 = ins.rs1 as usize; + let rs2 = ins.rs2 as usize; + match ins.opcode { RISCV_OP => { let name: &str; @@ -168,33 +181,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 name = names_op[ins.funct3 as usize]; } } - format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string()) + format!("{} {}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("slrii x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + format!("slrii {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } else { - format!("srai x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + format!("srai {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } } else if ins.funct3 == RISCV_OPI_SLLI { - format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) + format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } else { - format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) + format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) } }, RISCV_LUI => { - format!("lui x{}, 0x{:X}", ins.rd.to_string(), ins.imm31_12) + format!("lui {}, 0x{:X}", reg_x[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc x{}, {:X}", ins.rd.to_string(), ins.imm31_12) + format!("auipc {}, {:X}", reg_x[rd], ins.imm31_12) }, RISCV_JAL => { if ins.rd == 0 { format!("j {}", ins.imm31_12.to_string()) } else { - format!("jal x{}, {:X}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed)) + format!("jal {}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) } }, RISCV_JALR => { @@ -205,49 +218,49 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jr {:X}", ins.imm31_12) } } else { - format!("jalr {}, (r{})", ins.imm12_I_signed.to_string(), ins.rs1.to_string()) + format!("jalr {}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) } }, RISCV_BR => { - format!("{} r{} x{} {}", names_br[ins.funct3 as usize].to_string(), ins.rs1.to_string(), ins.rs2.to_string(), ins.imm13_signed.to_string()) + format!("{} {}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) }, RISCV_LD => { - format!("{} x{}, {}(x{})", names_ld[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.imm12_I_signed.to_string(), ins.rs1.to_string()) + format!("{} {}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) }, RISCV_ST => { - format!("{} x{}, {}(x{})", names_st[ins.funct3 as usize].to_string(), ins.rs2.to_string(), ins.imm12_S_signed.to_string(), ins.rs1.to_string()) + format!("{} {}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) }, RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srlwi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("srlwi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("srawi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("srawi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{} x{}, x{}, x{}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("{} x{}, x{}, x{}", names_opiw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) + format!("{} {}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w x{}, x{}, x{}", names_mul[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("{}w {}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { - format!("addw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("addw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("subw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("subw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else if ins.funct3 == RISCV_OPW_SRW { if ins.funct7 == RISCV_OPW_SRW_SRLW { - format!("srlw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("srlw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("sraw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("sraw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else { - format!("{} x{}, x{}, x{}", names_opw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) + format!("{} {}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) } } }, @@ -273,11 +286,11 @@ mod test { let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); - assert_eq!("sub r28, r17, r16", print::print(sub, 0)); - assert_eq!("xor r28, r17, r16", print::print(xor, 0)); - assert_eq!("srl r28, r17, r16", print::print(slr, 0)); - assert_eq!("sra r28, r17, r16", print::print(sra, 0)); - assert_eq!("add r28, r17, r16", print::print(add, 0)); + assert_eq!("sub t3, a7, a6", print::print(sub, 0)); + assert_eq!("xor t3, a7, a6", print::print(xor, 0)); + assert_eq!("srl t3, a7, a6", print::print(slr, 0)); + assert_eq!("sra t3, a7, a6", print::print(sra, 0)); + assert_eq!("add t3, a7, a6", print::print(add, 0)); } @@ -290,21 +303,21 @@ mod test { let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011); let andi = decode::decode(0b000000000000_10001_111_11100_0010011); - assert_eq!("andi x28, x17, 0", print::print(andi, 0)); - assert_eq!("addi x28, x17, 0", print::print(addi, 0)); - assert_eq!("slli x28, x17, 0", print::print(slli, 0)); - assert_eq!("slti x28, x17, 0", print::print(slti, 0)); - assert_eq!("sltiu x28, x17, 0", print::print(sltiu, 0)); - assert_eq!("xori x28, x17, 0", print::print(xori, 0)); - assert_eq!("ori x28, x17, 0", print::print(ori, 0)); + assert_eq!("andi t3, a7, 0", print::print(andi, 0)); + assert_eq!("addi t3, a7, 0", print::print(addi, 0)); + assert_eq!("slli t3, a7, 0", print::print(slli, 0)); + assert_eq!("slti t3, a7, 0", print::print(slti, 0)); + assert_eq!("sltiu t3, a7, 0", print::print(sltiu, 0)); + assert_eq!("xori t3, a7, 0", print::print(xori, 0)); + assert_eq!("ori t3, a7, 0", print::print(ori, 0)); } #[test] fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui x28, 0x710F8000", print::print(lui, 0)); - assert_eq!("lui x28, 0xF10F8000", print::print(lui_negatif, 0)); + assert_eq!("lui t3, 0x710F8000", print::print(lui, 0)); + assert_eq!("lui t3, 0xF10F8000", print::print(lui_negatif, 0)); } #[test] @@ -318,13 +331,13 @@ mod test { let ld = decode::decode(0b010111110000_10001_011_11100_0000011); let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); // TODO: imm négatif produit une erreur - assert_eq!("lb x28, 1520(x17)", print::print(lb, 0)); - assert_eq!("lh x28, 1520(x17)", print::print(lh, 0)); - assert_eq!("lw x28, 1520(x17)", print::print(lw, 0)); - assert_eq!("lbu x28, 1520(x17)", print::print(lbu, 0)); - assert_eq!("lhu x28, 1520(x17)", print::print(lhu, 0)); - assert_eq!("ld x28, 1520(x17)", print::print(ld, 0)); - assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0)); + assert_eq!("lb t3, 1520(a7)", print::print(lb, 0)); + assert_eq!("lh t3, 1520(a7)", print::print(lh, 0)); + assert_eq!("lw t3, 1520(a7)", print::print(lw, 0)); + assert_eq!("lbu t3, 1520(a7)", print::print(lbu, 0)); + assert_eq!("lhu t3, 1520(a7)", print::print(lhu, 0)); + assert_eq!("ld t3, 1520(a7)", print::print(ld, 0)); + assert_eq!("lwu t3, 1520(a7)", print::print(lwu, 0)); } #[test] @@ -334,20 +347,20 @@ mod test { let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); - assert_eq!("addw x28, x17, x16", print::print(addw, 0)); - assert_eq!("sllw x28, x17, x16", print::print(sllw, 0)); - assert_eq!("srlw x28, x17, x16", print::print(srlw, 0)); - assert_eq!("sraw x28, x17, x16", print::print(sraw, 0)); + assert_eq!("addw t3, a7, a6", print::print(addw, 0)); + assert_eq!("sllw t3, a7, a6", print::print(sllw, 0)); + assert_eq!("srlw t3, a7, a6", print::print(srlw, 0)); + assert_eq!("sraw t3, a7, a6", print::print(sraw, 0)); } #[test] fn test_opwi() { - let addwi: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); - let sllwi: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); + let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); + let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); - assert_eq!("addwi x28, x17, x0", print::print(addwi, 0)); - assert_eq!("slli x28, x17, x16", print::print(sllwi, 0)); - assert_eq!("srai x28, x17, 17", print::print(srai, 0)); + assert_eq!("addiw t3, a7, 0", print::print(addiw, 0)); + assert_eq!("slli t3, a7, a6", print::print(slliw, 0)); + assert_eq!("srai t3, a7, 17", print::print(srai, 0)); } @@ -359,12 +372,12 @@ mod test { let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); - assert_eq!("blt r17 x16 0", print::print(blt, 0)); - assert_eq!("bge r17 x16 0", print::print(bge, 0)); - assert_eq!("bltu r17 x16 0", print::print(bltu, 0)); - assert_eq!("bgeu r17 x16 0", print::print(bgeu, 0)); - assert_eq!("bne r17 x16 0", print::print(bne, 0)); - assert_eq!("beq r17 x16 0", print::print(beq, 0)); + assert_eq!("blt a7, a6, 0", print::print(blt, 0)); + assert_eq!("bge a7, a6, 0", print::print(bge, 0)); + assert_eq!("bltu a7, a6, 0", print::print(bltu, 0)); + assert_eq!("bgeu a7, a6, 0", print::print(bgeu, 0)); + assert_eq!("bne a7, a6, 0", print::print(bne, 0)); + assert_eq!("beq a7, a6, 0", print::print(beq, 0)); } } \ No newline at end of file From 802f80e96aa9e20734be4601f79780243cc00764 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 16 Nov 2022 17:37:04 +0100 Subject: [PATCH 026/128] Align with tabulations --- src/print.rs | 118 +++++++++++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/src/print.rs b/src/print.rs index 2fc2e65..b92b555 100644 --- a/src/print.rs +++ b/src/print.rs @@ -181,33 +181,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 name = names_op[ins.funct3 as usize]; } } - format!("{} {}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("slrii {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } else { - format!("srai {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } } else if ins.funct3 == RISCV_OPI_SLLI { - format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) } else { - format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) } }, RISCV_LUI => { - format!("lui {}, 0x{:X}", reg_x[rd], ins.imm31_12) + format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc {}, {:X}", reg_x[rd], ins.imm31_12) + format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12) }, RISCV_JAL => { if ins.rd == 0 { - format!("j {}", ins.imm31_12.to_string()) + format!("j\t{}", ins.imm31_12.to_string()) } else { - format!("jal {}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) + format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) } }, RISCV_JALR => { @@ -215,52 +215,52 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 if ins.rs1 == 1 { "ret".to_string() } else { - format!("jr {:X}", ins.imm31_12) + format!("jr\t{:X}", ins.imm31_12) } } else { - format!("jalr {}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) } }, RISCV_BR => { - format!("{} {}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) + format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) }, RISCV_LD => { - format!("{} {}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) }, RISCV_ST => { - format!("{} {}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) }, RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srlwi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("srawi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("{} {}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w {}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { - format!("addw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("subw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else if ins.funct3 == RISCV_OPW_SRW { if ins.funct7 == RISCV_OPW_SRW_SRLW { - format!("srlw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } else { - format!("sraw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) } } else { - format!("{} {}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) } } }, @@ -286,11 +286,11 @@ mod test { let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); - assert_eq!("sub t3, a7, a6", print::print(sub, 0)); - assert_eq!("xor t3, a7, a6", print::print(xor, 0)); - assert_eq!("srl t3, a7, a6", print::print(slr, 0)); - assert_eq!("sra t3, a7, a6", print::print(sra, 0)); - assert_eq!("add t3, a7, a6", print::print(add, 0)); + assert_eq!("sub\tt3, a7, a6", print::print(sub, 0)); + assert_eq!("xor\tt3, a7, a6", print::print(xor, 0)); + assert_eq!("srl\tt3, a7, a6", print::print(slr, 0)); + assert_eq!("sra\tt3, a7, a6", print::print(sra, 0)); + assert_eq!("add\tt3, a7, a6", print::print(add, 0)); } @@ -303,21 +303,21 @@ mod test { let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011); let andi = decode::decode(0b000000000000_10001_111_11100_0010011); - assert_eq!("andi t3, a7, 0", print::print(andi, 0)); - assert_eq!("addi t3, a7, 0", print::print(addi, 0)); - assert_eq!("slli t3, a7, 0", print::print(slli, 0)); - assert_eq!("slti t3, a7, 0", print::print(slti, 0)); - assert_eq!("sltiu t3, a7, 0", print::print(sltiu, 0)); - assert_eq!("xori t3, a7, 0", print::print(xori, 0)); - assert_eq!("ori t3, a7, 0", print::print(ori, 0)); + assert_eq!("andi\tt3, a7, 0", print::print(andi, 0)); + assert_eq!("addi\tt3, a7, 0", print::print(addi, 0)); + assert_eq!("slli\tt3, a7, 0", print::print(slli, 0)); + assert_eq!("slti\tt3, a7, 0", print::print(slti, 0)); + assert_eq!("sltiu\tt3, a7, 0", print::print(sltiu, 0)); + assert_eq!("xori\tt3, a7, 0", print::print(xori, 0)); + assert_eq!("ori\tt3, a7, 0", print::print(ori, 0)); } #[test] fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui t3, 0x710F8000", print::print(lui, 0)); - assert_eq!("lui t3, 0xF10F8000", print::print(lui_negatif, 0)); + assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0)); + assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0)); } #[test] @@ -330,14 +330,14 @@ mod test { let lhu = decode::decode(0b010111110000_10001_101_11100_0000011); let ld = decode::decode(0b010111110000_10001_011_11100_0000011); let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); - // TODO: imm négatif produit une erreur - assert_eq!("lb t3, 1520(a7)", print::print(lb, 0)); - assert_eq!("lh t3, 1520(a7)", print::print(lh, 0)); - assert_eq!("lw t3, 1520(a7)", print::print(lw, 0)); - assert_eq!("lbu t3, 1520(a7)", print::print(lbu, 0)); - assert_eq!("lhu t3, 1520(a7)", print::print(lhu, 0)); - assert_eq!("ld t3, 1520(a7)", print::print(ld, 0)); - assert_eq!("lwu t3, 1520(a7)", print::print(lwu, 0)); + + assert_eq!("lb\tt3, 1520(a7)", print::print(lb, 0)); + assert_eq!("lh\tt3, 1520(a7)", print::print(lh, 0)); + assert_eq!("lw\tt3, 1520(a7)", print::print(lw, 0)); + assert_eq!("lbu\tt3, 1520(a7)", print::print(lbu, 0)); + assert_eq!("lhu\tt3, 1520(a7)", print::print(lhu, 0)); + assert_eq!("ld\tt3, 1520(a7)", print::print(ld, 0)); + assert_eq!("lwu\tt3, 1520(a7)", print::print(lwu, 0)); } #[test] @@ -347,10 +347,10 @@ mod test { let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); - assert_eq!("addw t3, a7, a6", print::print(addw, 0)); - assert_eq!("sllw t3, a7, a6", print::print(sllw, 0)); - assert_eq!("srlw t3, a7, a6", print::print(srlw, 0)); - assert_eq!("sraw t3, a7, a6", print::print(sraw, 0)); + assert_eq!("addw\tt3, a7, a6", print::print(addw, 0)); + assert_eq!("sllw\tt3, a7, a6", print::print(sllw, 0)); + assert_eq!("srlw\tt3, a7, a6", print::print(srlw, 0)); + assert_eq!("sraw\tt3, a7, a6", print::print(sraw, 0)); } #[test] @@ -358,9 +358,9 @@ mod test { let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); - assert_eq!("addiw t3, a7, 0", print::print(addiw, 0)); - assert_eq!("slli t3, a7, a6", print::print(slliw, 0)); - assert_eq!("srai t3, a7, 17", print::print(srai, 0)); + assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0)); + assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0)); + assert_eq!("srai\tt3, a7, 17", print::print(srai, 0)); } @@ -372,12 +372,12 @@ mod test { let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); - assert_eq!("blt a7, a6, 0", print::print(blt, 0)); - assert_eq!("bge a7, a6, 0", print::print(bge, 0)); - assert_eq!("bltu a7, a6, 0", print::print(bltu, 0)); - assert_eq!("bgeu a7, a6, 0", print::print(bgeu, 0)); - assert_eq!("bne a7, a6, 0", print::print(bne, 0)); - assert_eq!("beq a7, a6, 0", print::print(beq, 0)); + assert_eq!("blt\ta7, a6, 0", print::print(blt, 0)); + assert_eq!("bge\ta7, a6, 0", print::print(bge, 0)); + assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0)); + assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0)); + assert_eq!("bne\ta7, a6, 0", print::print(bne, 0)); + assert_eq!("beq\ta7, a6, 0", print::print(beq, 0)); } } \ No newline at end of file From a4230cd3577b84d232a72d49eef1a68765ab33a1 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 16 Nov 2022 17:48:55 +0100 Subject: [PATCH 027/128] RISC OP MUL and DIV + changement prototype OneInstruction --- src/machine.rs | 124 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 84 insertions(+), 40 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 2bb70f7..788db98 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -31,6 +31,15 @@ impl Machine { let mut unsigned_reg1 : u64 = 0; let mut unsigned_reg2 : u64 = 0; + let mut long_result : i128 = 0; + + /*__int128 longResult; + int32_t localDataa, localDatab; + int64_t localLongResult; + uint32_t localDataaUnsigned, localDatabUnsigned; + int32_t localResult; + float localFloat; + uint64_t value;*/ if machine.instructions.len() <= machine.pc as usize { println!("ERROR : number max of instructions rushed"); @@ -79,49 +88,84 @@ impl Machine { }, RISCV_OP => { - match inst.funct3 { - RISCV_OP_ADD => { - // RISCV_OP_ADD_ADD inaccessible - /*if (inst.funct7 == RISCV_OP_ADD_ADD) { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; - //} - }, - RISCV_OP_SLL => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); - }, - RISCV_OP_SLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { - machine.int_reg[inst.rd as usize] = 1; - } else { - machine.int_reg[inst.rd as usize] = 0; + if(inst.funct7 == 1){ + match inst.funct3 { + RISCV_OP_M_MUL => { + long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; + machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32; + }, + RISCV_OP_M_MULH => { + long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; + + }, + RISCV_OP_M_MULHSU => { + unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + }, + // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve + /* + * VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++) + * WHAT DA HECK + */ + RISCV_OP_M_MULHU => { + unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; + unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + long_result = (unsigned_reg1 * unsigned_reg2) as i128; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + }, + RISCV_OP_M_DIV => { + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]); } - }, - RISCV_OP_SLTU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; - if unsigned_reg1 < unsigned_reg2 { - machine.int_reg[inst.rd as usize] = 1; - } else { - machine.int_reg[inst.rd as usize] = 0; + _ => { + println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); } - }, - RISCV_OP_XOR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; - }, - RISCV_OP_SR => { - // RISCV_OP_SR_SRL inaccessible - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); - }, - RISCV_OP_OR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; - }, - RISCV_OP_AND => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; - }, - _ => { - println!("RISCV_OP undefined case\n"); } + } else { + match inst.funct3 { + RISCV_OP_ADD => { + // RISCV_OP_ADD_ADD inaccessible + /*if (inst.funct7 == RISCV_OP_ADD_ADD) { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; + //} + }, + RISCV_OP_SLL => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); + }, + RISCV_OP_SLT => { + if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + machine.int_reg[inst.rd as usize] = 1; + } else { + machine.int_reg[inst.rd as usize] = 0; + } + }, + RISCV_OP_SLTU => { + unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; + unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + if unsigned_reg1 < unsigned_reg2 { + machine.int_reg[inst.rd as usize] = 1; + } else { + machine.int_reg[inst.rd as usize] = 0; + } + }, + RISCV_OP_XOR => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; + }, + RISCV_OP_SR => { + // RISCV_OP_SR_SRL inaccessible + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); + }, + RISCV_OP_OR => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; + }, + RISCV_OP_AND => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; + }, + _ => { + println!("RISCV_OP undefined case\n"); + } + }//LA } } _ => { println!("{} opcode non géré", inst.opcode)}, From d021fc3565cb9984645b7db7439f4bbc09b59c19 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 16 Nov 2022 17:59:09 +0100 Subject: [PATCH 028/128] OPW instructions --- src/machine.rs | 80 ++++++++++++++++++++++++++++++++++++++++++++++++-- src/print.rs | 32 ++++++++++++++++++++ 2 files changed, 110 insertions(+), 2 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 2bb70f7..58f66a5 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -9,7 +9,8 @@ pub struct Machine { pub pc : u32, pub int_reg : [u32 ; 32], pub instructions : [u32 ; 100], - pub main_memory : [u8 ; MEM_SIZE] + pub main_memory : [u8 ; MEM_SIZE], + pub shiftmask : [u32 ; 32] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -18,12 +19,21 @@ pub struct Machine { impl Machine { pub fn _init_machine() -> Machine { + let mut shiftmask : [u32 ; 32] = [0 ; 32]; + let mut value : u32 = 0xffff; + + value = (value << 16) + value; + for i in 0..32 { + shiftmask[i] = value; + value = value >> 1; + } Machine { pc : 0, instructions : [0 ; 100], int_reg : [0 ; 32], - main_memory : [0 ; MEM_SIZE] + main_memory : [0 ; MEM_SIZE], + shiftmask : shiftmask } } @@ -68,6 +78,13 @@ impl Machine { }, RISCV_OPI_SLLI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + }, + RISCV_OPI_SRI => { + if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize]; + } else { // SRAI + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt); + } } _ => { println!("{} inconnu", inst.funct3); } } @@ -123,6 +140,65 @@ impl Machine { println!("RISCV_OP undefined case\n"); } } + }, + //****************************************************************************************** + // Treatment for: OPW INSTRUCTIONS + RISCV_OPW => { + if inst.funct7 == 1 { + let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + + // Match case for multiplication operations (in standard extension RV32M) + match inst.funct3 { + RISCV_OPW_M_MULW => { + machine.int_reg[inst.rd as usize] = localDataa * localDatab; + }, + RISCV_OPW_M_DIVW => { + machine.int_reg[inst.rd as usize] = localDataa / localDatab; + }, + RISCV_OPW_M_DIVUW => { + machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned; + }, + RISCV_OPW_M_REMW => { + machine.int_reg[inst.rd as usize] = localDataa % localDatab; + }, + RISCV_OPW_M_REMUW => { + machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned; + }, + _ => { + println!("this instruction ({}) doesn't exists", inst.value); + } + } + } else { + let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + + // Match case for base OP operation + match inst.funct3 { + RISCV_OPW_ADDSUBW => { + if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { + machine.int_reg[inst.rd as usize] = localDataa + localDatab; + } else { // SUBW + machine.int_reg[inst.rd as usize] = localDataa - localDatab; + } + }, + RISCV_OPW_SLLW => { + machine.int_reg[inst.rd as usize] = localDataa << (localDatab & 0x1f); + }, + RISCV_OPW_SRW => { + if inst.funct7 == RISCV_OPW_SRW_SRLW { + machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f) & machine.shiftmask[32 + localDatab as usize]; + } else { // SRAW + machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f); + } + }, + _ => { + println!("this instruction ({}) doesn't exists", inst.value); + } + } + } } _ => { println!("{} opcode non géré", inst.opcode)}, } diff --git a/src/print.rs b/src/print.rs index 4aa70b0..788a6bd 100644 --- a/src/print.rs +++ b/src/print.rs @@ -130,6 +130,38 @@ pub const RISCV_FP_FCMP_FLE: u8 = 0; pub const RISCV_FP_FMVW: u8 = 0x78; +pub const RISCV_OP_M: u8 = 0x1; + +pub const RISCV_OP_M_MUL: u8 = 0x0; +pub const RISCV_OP_M_MULH: u8 = 0x1; +pub const RISCV_OP_M_MULHSU: u8 = 0x2; +pub const RISCV_OP_M_MULHU: u8 = 0x3; +pub const RISCV_OP_M_DIV: u8 = 0x4; +pub const RISCV_OP_M_DIVU: u8 = 0x5; +pub const RISCV_OP_M_REM: u8 = 0x6; +pub const RISCV_OP_M_REMU: u8 = 0x7; + +pub const RISCV_OPW_M_MULW: u8 = 0x0; +pub const RISCV_OPW_M_DIVW: u8 = 0x4; +pub const RISCV_OPW_M_DIVUW: u8 = 0x5; +pub const RISCV_OPW_M_REMW: u8 = 0x6; +pub const RISCV_OPW_M_REMUW: u8 = 0x7; + +pub const RISCV_FENCE: u8 = 0x0f; + +pub const RISCV_ATOM: u8 = 0x2f; +pub const RISCV_ATOM_LR: u8 = 0x2; +pub const RISCV_ATOM_SC: u8 = 0x3; +pub const RISCV_ATOM_SWAP: u8 = 0x1; +pub const RISCV_ATOM_ADD: u8 = 0; +pub const RISCV_ATOM_XOR: u8 = 0x4; +pub const RISCV_ATOM_AND: u8 = 0xc; +pub const RISCV_ATOM_OR: u8 = 0x8; +pub const RISCV_ATOM_MIN: u8 = 0x10; +pub const RISCV_ATOM_MAX: u8 = 0x14; +pub const RISCV_ATOM_MINU: u8 = 0x18; +pub const RISCV_ATOM_MAXU: u8 = 0x1c; + const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; From 233d928b6fd36e5ba12363cb8c6115c0b8e84906 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Mon, 21 Nov 2022 13:17:42 +0100 Subject: [PATCH 029/128] implemented run function to use one-instruction for several instruction --- src/machine.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/machine.rs b/src/machine.rs index be92662..c71ccd2 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -37,6 +37,13 @@ impl Machine { } } + pub fn run(machine : Machine){ + let mut m = machine; + loop{ + Machine::one_instruction(&mut m); + } + } + pub fn one_instruction(machine :&mut Machine) { let mut unsigned_reg1 : u64 = 0; From bb46fae06bc1f4bfe6b9008c643ba316b0385460 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Mon, 21 Nov 2022 13:21:48 +0100 Subject: [PATCH 030/128] added some commentaries --- src/machine.rs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/machine.rs b/src/machine.rs index c71ccd2..1d6a0cb 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -37,6 +37,11 @@ impl Machine { } } + + /* + execute the instructions table of a machine putted in param + @param machine which contains a table of instructions + */ pub fn run(machine : Machine){ let mut m = machine; loop{ @@ -44,6 +49,10 @@ impl Machine { } } + /* + execute the current instruction + @param machine which contains a table of instructions and a pc to the actual instruction + */ pub fn one_instruction(machine :&mut Machine) { let mut unsigned_reg1 : u64 = 0; From ad960a46e0e5b4297286efd0b44eba72b86880a7 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 23 Nov 2022 16:04:21 +0100 Subject: [PATCH 031/128] Comments has been standardized, remove some warnings --- src/machine.rs | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 1d6a0cb..c055377 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,7 +1,7 @@ use crate::decode::*; use crate::print::*; -// doit disparaitre +/// doit disparaitre const MEM_SIZE : usize= 4096; @@ -38,10 +38,11 @@ impl Machine { } - /* - execute the instructions table of a machine putted in param - @param machine which contains a table of instructions - */ + /// Execute the instructions table of a machine putted in param + /// + /// ### Parameters + /// + /// - **machine** which contains a table of instructions pub fn run(machine : Machine){ let mut m = machine; loop{ @@ -49,10 +50,11 @@ impl Machine { } } - /* - execute the current instruction - @param machine which contains a table of instructions and a pc to the actual instruction - */ + /// execute the current instruction + /// + /// ### Parameters + /// + /// - **machine** which contains a table of instructions and a pc to the actual instruction pub fn one_instruction(machine :&mut Machine) { let mut unsigned_reg1 : u64 = 0; @@ -108,7 +110,7 @@ impl Machine { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize]; } else { // SRAI - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt); + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; } } _ => { println!("{} inconnu", inst.funct3); } @@ -121,7 +123,7 @@ impl Machine { }, RISCV_OP => { - if(inst.funct7 == 1){ + if inst.funct7 == 1{ match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; @@ -148,7 +150,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; }, RISCV_OP_M_DIV => { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]); + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; } _ => { println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); @@ -232,26 +234,26 @@ impl Machine { } } } else { - let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; // Match case for base OP operation match inst.funct3 { RISCV_OPW_ADDSUBW => { if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { - machine.int_reg[inst.rd as usize] = localDataa + localDatab; + machine.int_reg[inst.rd as usize] = local_dataa + local_datab; } else { // SUBW - machine.int_reg[inst.rd as usize] = localDataa - localDatab; + machine.int_reg[inst.rd as usize] = local_dataa - local_datab; } }, RISCV_OPW_SLLW => { - machine.int_reg[inst.rd as usize] = localDataa << (localDatab & 0x1f); + machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f); }, RISCV_OPW_SRW => { if inst.funct7 == RISCV_OPW_SRW_SRLW { - machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f) & machine.shiftmask[32 + localDatab as usize]; + machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize]; } else { // SRAW - machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f); + machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f); } }, _ => { From f897276c4370e62754a4adc6f916fa1a825e1151 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 23 Nov 2022 16:29:02 +0100 Subject: [PATCH 032/128] change to 64bit --- src/decode.rs | 4 ++-- src/machine.rs | 50 ++++++++++++++++++++++++++++++-------------------- 2 files changed, 32 insertions(+), 22 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index 68d0e2f..32dc030 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -3,7 +3,7 @@ use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations #[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules) #[derive(Debug)] pub struct Instruction { - pub value : u32, + pub value : u64, pub opcode : u8, pub rs1 : u8, @@ -31,7 +31,7 @@ pub struct Instruction { } #[allow(non_snake_case)] -pub fn decode(val : u32) -> Instruction { +pub fn decode(val : u64) -> Instruction { let value = val; diff --git a/src/machine.rs b/src/machine.rs index 1d6a0cb..4580ff4 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -4,13 +4,12 @@ use crate::print::*; // doit disparaitre const MEM_SIZE : usize= 4096; - pub struct Machine { - pub pc : u32, - pub int_reg : [u32 ; 32], - pub instructions : [u32 ; 100], + pub pc : u64, + pub int_reg : [u64 ; 32], + pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], - pub shiftmask : [u32 ; 32] + pub shiftmask : [u64 ; 64] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -19,11 +18,11 @@ pub struct Machine { impl Machine { pub fn _init_machine() -> Machine { - let mut shiftmask : [u32 ; 32] = [0 ; 32]; - let mut value : u32 = 0xffff; + let mut shiftmask : [u64 ; 64] = [0 ; 64]; + let mut value : u64 = 0xffffffff; - value = (value << 16) + value; - for i in 0..32 { + value = (value << 32) + value; + for i in 0..64 { shiftmask[i] = value; value = value >> 1; } @@ -78,28 +77,39 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12; + machine.int_reg[inst.rd as usize] = inst.imm31_12 as u64; }, - + RISCV_AUIPC => { + machine.int_reg[inst.rd as usize] = machine.pc - 4 + inst.imm31_12 as u64; + }, + RISCV_JAL => { + machine.int_reg[inst.rd as usize] = machine.pc; + machine.pc += inst.imm21_1_signed as u64 - 4; + }, + RISCV_JALR => { + let tmp = machine.pc; + machine.pc = (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg[inst.rd as usize] = tmp; + } //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64; }, RISCV_OPI_SLTI => { machine.int_reg[inst.rd as usize] = - if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 }; + if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u64 { 1 } else { 0 }; }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u64; }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u64; }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u64; }, RISCV_OPI_SLLI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; @@ -117,7 +127,7 @@ impl Machine { RISCV_JAL => { machine.int_reg[inst.rd as usize] = machine.pc; - machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u32); + machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u64); }, RISCV_OP => { @@ -125,7 +135,7 @@ impl Machine { match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u64; }, RISCV_OP_M_MULH => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; @@ -134,7 +144,7 @@ impl Machine { RISCV_OP_M_MULHSU => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -145,7 +155,7 @@ impl Machine { unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; }, RISCV_OP_M_DIV => { machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]); From 4fa691a568dfa10c92895d91b3fb855dfa866ef6 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 23 Nov 2022 18:04:35 +0100 Subject: [PATCH 033/128] LOAD and BRANCH instructions --- src/machine.rs | 140 +++++++++++++++++++++++++++++++++++++++++-------- src/main.rs | 9 +++- 2 files changed, 125 insertions(+), 24 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index d0a5385..b77bd41 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -6,7 +6,7 @@ const MEM_SIZE : usize= 4096; pub struct Machine { pub pc : u64, - pub int_reg : [u64 ; 32], + pub int_reg : [i64 ; 32], pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -36,6 +36,33 @@ impl Machine { } } + /// Read from main memory of the machine + /// + /// ### Parameters + /// + /// - **machine** which contains the main memory + /// - **size** the number of bytes to read (1, 2, 4, 8) + /// - **address** in the memory to read + pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { + if size != 1 && size != 2 && size != 4 && size != 8 { + println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); + } + + let mut ret : u64 = machine.main_memory[address] as u64; + if size == 2 || size == 4 || size == 8 { + ret = ret << 8; + ret += machine.main_memory[address + 1] as u64; + } + if size == 4 || size == 8 { + ret = ret << 8; + ret += machine.main_memory[address + 2] as u64; + } + if size == 8 { + ret = ret << 8; + ret += machine.main_memory[address + 3] as u64; + } + return ret; + } /// Execute the instructions table of a machine putted in param /// @@ -79,46 +106,120 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12 as u64; + machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; }, RISCV_AUIPC => { - machine.int_reg[inst.rd as usize] = machine.pc - 4 + inst.imm31_12 as u64; + machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; }, RISCV_JAL => { - machine.int_reg[inst.rd as usize] = machine.pc; + machine.int_reg[inst.rd as usize] = machine.pc as i64; machine.pc += inst.imm21_1_signed as u64 - 4; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64) & 0xfffffffe; - machine.int_reg[inst.rd as usize] = tmp; - } + machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg[inst.rd as usize] = tmp as i64; + }, + + //****************************************************************************************** + // Treatment for: BRANCH INSTRUCTIONS + RISCV_BR => { + match inst.funct3 { + RISCV_BR_BEQ => { + if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + RISCV_BR_BNE => { + if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + RICV_BR_BLT => { + if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + RICV_BR_BGE => { + if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + RICV_BR_BLTU => { + if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + RICV_BR_BGEU => { + if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + machine.pc += inst.imm13_signed as u64 - 4; + } + }, + _ => { + println!("In BR switch case, this should never happen... Instr was {}", inst.value); + } + } + }, + + //****************************************************************************************** + // Treatment for: LOAD INSTRUCTIONS + RISCV_LD => { + match inst.funct3 { + RISCV_LD_LB => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + RISCV_LD_LH => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + RISCV_LD_LW => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + RISCV_LD_LD => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + + // same thing three opration ? + RISCV_LD_LBU => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + RISCV_LD_LHU => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + RISCV_LD_LWU => { + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + }, + _ => { + println!("In LD switch case, this should never happen... Instr was {}", inst.value); + } + } + }, + //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; }, RISCV_OPI_SLTI => { machine.int_reg[inst.rd as usize] = - if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u64 { 1 } else { 0 }; + if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 }; }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u64; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u64; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u64; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; }, RISCV_OPI_SLLI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize]; + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; } else { // SRAI machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; } @@ -127,17 +228,12 @@ impl Machine { } }, - RISCV_JAL => { - machine.int_reg[inst.rd as usize] = machine.pc; - machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u64); - }, - RISCV_OP => { if inst.funct7 == 1{ match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u64; + machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; }, RISCV_OP_M_MULH => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; @@ -146,7 +242,7 @@ impl Machine { RISCV_OP_M_MULHSU => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -157,7 +253,7 @@ impl Machine { unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; }, RISCV_OP_M_DIV => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; @@ -261,7 +357,7 @@ impl Machine { }, RISCV_OPW_SRW => { if inst.funct7 == RISCV_OPW_SRW_SRLW { - machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize]; + machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64; } else { // SRAW machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f); } diff --git a/src/main.rs b/src/main.rs index 8a37ccd..4e93275 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,6 +5,11 @@ use machine::Machine; fn main() { let mut m = Machine::_init_machine(); - m.instructions[0] = 0x37; - Machine::one_instruction(&mut m); + m.main_memory[4] = 43; + m.main_memory[5] = 150; + let a : u8 = 128; + let b : i8 = a as i8; + let c : u8 = b as u8; + println!("aaa {}", c); + println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4)); } From 27cd7d35c7bb73658981f072fe070a02176fb4b7 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 7 Dec 2022 17:09:53 +0100 Subject: [PATCH 034/128] fix ADD_ADD --- src/machine.rs | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index b77bd41..2453d23 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -102,8 +102,7 @@ impl Machine { let inst : Instruction = decode(machine.instructions[machine.pc as usize]); - machine.pc += 4; - + match inst.opcode { RISCV_LUI => { machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; @@ -194,6 +193,8 @@ impl Machine { } }, + //TODO store instructions + //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { @@ -265,11 +266,11 @@ impl Machine { } else { match inst.funct3 { RISCV_OP_ADD => { - // RISCV_OP_ADD_ADD inaccessible - /*if (inst.funct7 == RISCV_OP_ADD_ADD) { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; - //} + if (inst.funct7 == RISCV_OP_ADD_ADD) { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; + } else { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; + } }, RISCV_OP_SLL => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); @@ -371,6 +372,7 @@ impl Machine { _ => { println!("{} opcode non géré", inst.opcode)}, } + machine.pc += 4; } } From b1909e3280e05ae6936eec8ff0e559186d3d10e0 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 11 Jan 2023 14:58:12 +0100 Subject: [PATCH 035/128] Moving files to simulator module --- src/main.rs | 7 +++---- src/{ => simulator}/decode.rs | 0 src/{ => simulator}/machine.rs | 3 +-- src/simulator/mod.rs | 3 +++ src/{ => simulator}/print.rs | 4 ++-- 5 files changed, 9 insertions(+), 8 deletions(-) rename src/{ => simulator}/decode.rs (100%) rename src/{ => simulator}/machine.rs (99%) create mode 100644 src/simulator/mod.rs rename src/{ => simulator}/print.rs (99%) diff --git a/src/main.rs b/src/main.rs index 4e93275..953914e 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,7 +1,6 @@ -mod decode; -mod print; -mod machine; -use machine::Machine; +mod simulator; + +use simulator::machine::Machine; fn main() { let mut m = Machine::_init_machine(); diff --git a/src/decode.rs b/src/simulator/decode.rs similarity index 100% rename from src/decode.rs rename to src/simulator/decode.rs diff --git a/src/machine.rs b/src/simulator/machine.rs similarity index 99% rename from src/machine.rs rename to src/simulator/machine.rs index 2453d23..42e19f4 100644 --- a/src/machine.rs +++ b/src/simulator/machine.rs @@ -1,5 +1,4 @@ -use crate::decode::*; -use crate::print::*; +use super::{decode::{Instruction, decode}, print::*}; /// doit disparaitre const MEM_SIZE : usize= 4096; diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs new file mode 100644 index 0000000..581621e --- /dev/null +++ b/src/simulator/mod.rs @@ -0,0 +1,3 @@ +pub mod machine; +pub mod decode; +pub mod print; \ No newline at end of file diff --git a/src/print.rs b/src/simulator/print.rs similarity index 99% rename from src/print.rs rename to src/simulator/print.rs index c80cf9c..99ce2d0 100644 --- a/src/print.rs +++ b/src/simulator/print.rs @@ -1,6 +1,6 @@ #![allow(dead_code)] #![allow(unused_variables)] -use crate::decode::Instruction; +use super::decode::{Instruction}; pub const RISCV_LUI: u8 = 0x37; @@ -307,8 +307,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] mod test { + use crate::simulator::{decode, print}; - use crate::{print, decode}; #[test] fn test_op() { From 022388963bbbcba623868b9c47ab378003796c97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:04:54 +0100 Subject: [PATCH 036/128] Fixed clippy errors --- src/machine.rs | 52 +++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index 2453d23..59da0ef 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -22,8 +22,8 @@ impl Machine { let mut value : u64 = 0xffffffff; value = (value << 32) + value; - for i in 0..64 { - shiftmask[i] = value; + for item in &mut shiftmask { + *item = value; value = value >> 1; } @@ -32,7 +32,7 @@ impl Machine { instructions : [0 ; 100], int_reg : [0 ; 32], main_memory : [0 ; MEM_SIZE], - shiftmask : shiftmask + shiftmask } } @@ -50,18 +50,18 @@ impl Machine { let mut ret : u64 = machine.main_memory[address] as u64; if size == 2 || size == 4 || size == 8 { - ret = ret << 8; + ret <<= 8; ret += machine.main_memory[address + 1] as u64; } if size == 4 || size == 8 { - ret = ret << 8; + ret <<= 8; ret += machine.main_memory[address + 2] as u64; } if size == 8 { - ret = ret << 8; + ret <<= 8; ret += machine.main_memory[address + 3] as u64; } - return ret; + ret } /// Execute the instructions table of a machine putted in param @@ -83,14 +83,14 @@ impl Machine { /// - **machine** which contains a table of instructions and a pc to the actual instruction pub fn one_instruction(machine :&mut Machine) { - let mut unsigned_reg1 : u64 = 0; - let mut unsigned_reg2 : u64 = 0; - let mut long_result : i128 = 0; + let unsigned_reg1 : u64; + let unsigned_reg2 : u64; + let long_result : i128; /*__int128 longResult; - int32_t localDataa, localDatab; + int32_t local_data_a, local_data_b; int64_t localLongResult; - uint32_t localDataaUnsigned, localDatabUnsigned; + uint32_t local_data_aUnsigned, local_data_bUnsigned; int32_t localResult; float localFloat; uint64_t value;*/ @@ -134,22 +134,22 @@ impl Machine { machine.pc += inst.imm13_signed as u64 - 4; } }, - RICV_BR_BLT => { + RISCV_BR_BLT => { if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { machine.pc += inst.imm13_signed as u64 - 4; } }, - RICV_BR_BGE => { + RISCV_BR_BGE => { if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { machine.pc += inst.imm13_signed as u64 - 4; } }, - RICV_BR_BLTU => { + RISCV_BR_BLTU => { if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { machine.pc += inst.imm13_signed as u64 - 4; } }, - RICV_BR_BGEU => { + RISCV_BR_BGEU => { if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { machine.pc += inst.imm13_signed as u64 - 4; } @@ -266,7 +266,7 @@ impl Machine { } else { match inst.funct3 { RISCV_OP_ADD => { - if (inst.funct7 == RISCV_OP_ADD_ADD) { + if inst.funct7 == RISCV_OP_ADD_ADD { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; } else { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; @@ -314,27 +314,27 @@ impl Machine { // Treatment for: OPW INSTRUCTIONS RISCV_OPW => { if inst.funct7 == 1 { - let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; - let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; + let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; // Match case for multiplication operations (in standard extension RV32M) match inst.funct3 { RISCV_OPW_M_MULW => { - machine.int_reg[inst.rd as usize] = localDataa * localDatab; + machine.int_reg[inst.rd as usize] = local_data_a * local_data_b; }, RISCV_OPW_M_DIVW => { - machine.int_reg[inst.rd as usize] = localDataa / localDatab; + machine.int_reg[inst.rd as usize] = local_data_a / local_data_b; }, RISCV_OPW_M_DIVUW => { - machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned; + machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned; }, RISCV_OPW_M_REMW => { - machine.int_reg[inst.rd as usize] = localDataa % localDatab; + machine.int_reg[inst.rd as usize] = local_data_a % local_data_b; }, RISCV_OPW_M_REMUW => { - machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned; + machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned; }, _ => { println!("this instruction ({}) doesn't exists", inst.value); From fe2fe40a758307434a7701119867c26238a65293 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:31:52 +0100 Subject: [PATCH 037/128] Cleaned up cargo clippy warnings on print.rs --- src/simulator/print.rs | 116 ++++++++++++++++++++--------------------- 1 file changed, 57 insertions(+), 59 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 99ce2d0..47cb58a 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -163,22 +163,22 @@ pub const RISCV_ATOM_MINU: u8 = 0x18; pub const RISCV_ATOM_MAXU: u8 = 0x1c; -const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; -const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; -const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; -const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; -const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; -const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; -const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; -const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; +const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; +const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; +const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; +const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; +const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"]; +const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; +const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; +const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; // Register name mapping -const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? +const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"]; -const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", +const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"]; @@ -193,53 +193,51 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_OP => { let name: &str; if ins.funct7 == 1 { // Use mul array - name = names_mul[ins.funct3 as usize] - } else { - if ins.funct3 == RISCV_OP_ADD { - // Add or Sub - if ins.funct7 == RISCV_OP_ADD_ADD { - name = "add"; - } else { - name = "sub"; - } - } else if ins.funct3 == RISCV_OP_SR { - // Srl or Sra - if ins.funct7 == RISCV_OP_SR_SRL { - name = "srl"; - } else { - name = "sra"; - } + name = NAMES_MUL[ins.funct3 as usize] + } else if ins.funct3 == RISCV_OP_ADD { + // Add or Sub + if ins.funct7 == RISCV_OP_ADD_ADD { + name = "add"; } else { - name = names_op[ins.funct3 as usize]; + name = "sub"; } + } else if ins.funct3 == RISCV_OP_SR { + // Srl or Sra + if ins.funct7 == RISCV_OP_SR_SRL { + name = "srl"; + } else { + name = "sra"; + } + } else { + name = NAMES_OP[ins.funct3 as usize]; } - format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("slrii\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } } else if ins.funct3 == RISCV_OPI_SLLI { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_LUI => { - format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12) + format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12) + format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { if ins.rd == 0 { - format!("j\t{}", ins.imm31_12.to_string()) + format!("j\t{}", ins.imm31_12) } else { - format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) + format!("jal\t{}, {:X}", REG_X[rd], (pc - 4 + ins.imm21_1_signed)) } }, RISCV_JALR => { @@ -250,50 +248,48 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jr\t{:X}", ins.imm31_12) } } else { - format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1]) } }, RISCV_BR => { - format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed) }, RISCV_LD => { - format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_ST => { - format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1]) }, RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srlwi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srawi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - if ins.funct3 == RISCV_OP_ADD { - if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { - format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } - } else if ins.funct3 == RISCV_OPW_SRW { - if ins.funct7 == RISCV_OPW_SRW_SRLW { - format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } + format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + } else if ins.funct3 == RISCV_OP_ADD { + if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { + format!("addw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("subw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } + } else if ins.funct3 == RISCV_OPW_SRW { + if ins.funct7 == RISCV_OPW_SRW_SRLW { + format!("srlw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + } else { + format!("sraw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + } + } else { + format!("{}\t{}, {}, {}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } }, RISCV_SYSTEM => { @@ -307,6 +303,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] mod test { + + #![allow(clippy::unusual_byte_groupings)] use crate::simulator::{decode, print}; From 7649fae750113cf46323cacd16ca1c7d611c93a4 Mon Sep 17 00:00:00 2001 From: Aelbahri Date: Wed, 11 Jan 2023 15:33:22 +0100 Subject: [PATCH 038/128] warrning fixed --- src/simulator/decode.rs | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/simulator/decode.rs b/src/simulator/decode.rs index 32dc030..dea62b6 100644 --- a/src/simulator/decode.rs +++ b/src/simulator/decode.rs @@ -64,32 +64,32 @@ pub fn decode(val : u64) -> Instruction { let shamt = ((val >> 20) & 0x3f) as u8; Instruction { - value : value, + value, - opcode : opcode, - rs1 : rs1, - rs2 : rs2, - rs3 : rs3, - rd : rd, - funct7 : funct7, - funct7_smaller : funct7_smaller, + opcode, + rs1, + rs2, + rs3, + rd, + funct7, + funct7_smaller, - funct3 : funct3, - imm12_I : imm12_I, - imm12_S : imm12_S, + funct3, + imm12_I, + imm12_S, - imm12_I_signed : imm12_I_signed, - imm12_S_signed : imm12_S_signed, + imm12_I_signed, + imm12_S_signed, - imm13 : imm13, - imm13_signed : imm13_signed, + imm13, + imm13_signed, - imm31_12 : imm31_12, - imm31_12_signed : imm31_12_signed, + imm31_12, + imm31_12_signed, - imm21_1 : imm21_1, - imm21_1_signed : imm21_1_signed, + imm21_1, + imm21_1_signed, - shamt : shamt + shamt } } \ No newline at end of file From 5c375633229a3930d49c1fc6cd75f266b84d5ce3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:34:12 +0100 Subject: [PATCH 039/128] =?UTF-8?q?=F0=9F=9A=A8=20Cleaned=20up=20clippy=20?= =?UTF-8?q?warnings=20for=20machine.rs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/simulator/machine.rs | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 57f4550..57fd15e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -23,7 +23,7 @@ impl Machine { value = (value << 32) + value; for item in &mut shiftmask { *item = value; - value = value >> 1; + value >>= 1; } Machine { @@ -202,8 +202,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; }, RISCV_OPI_SLTI => { - machine.int_reg[inst.rd as usize] = - if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 }; + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; }, RISCV_OPI_XORI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; @@ -378,6 +377,5 @@ impl Machine { #[cfg(test)] mod test { - use super::Machine; } From ee8762fdb84667aa12fb030a37632e1506218073 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 11 Jan 2023 15:34:51 +0100 Subject: [PATCH 040/128] read_memory now panic instead of just displaying the error and continue the execution --- src/simulator/machine.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 57f4550..d63ea1e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -44,7 +44,7 @@ impl Machine { /// - **address** in the memory to read pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { if size != 1 && size != 2 && size != 4 && size != 8 { - println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); + panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); } let mut ret : u64 = machine.main_memory[address] as u64; @@ -379,5 +379,5 @@ impl Machine { #[cfg(test)] mod test { use super::Machine; - + } From c4aede53719864f73b59abdd769e1fd78bfcd0fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:39:40 +0100 Subject: [PATCH 041/128] =?UTF-8?q?=F0=9F=9A=A8=20Removed=20more=20clippy?= =?UTF-8?q?=20warnings=20from=20decode.rs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/simulator/decode.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/decode.rs b/src/simulator/decode.rs index dea62b6..91c8651 100644 --- a/src/simulator/decode.rs +++ b/src/simulator/decode.rs @@ -41,7 +41,7 @@ pub fn decode(val : u64) -> Instruction { let rs3 = ((val >> 27) & 0x1f) as u8; let rd = ((val >> 7) & 0x1f) as u8; let funct7 = ((val >> 25) & 0x7f) as u8; - let funct7_smaller = (funct7 & 0x3e) as u8; + let funct7_smaller = funct7 & 0x3e; let funct3 = ((val >> 12) & 0x7) as u8; let imm12_I = ((val >> 20) & 0xfff) as u16; @@ -52,7 +52,7 @@ pub fn decode(val : u64) -> Instruction { let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) + ((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16; - let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 } as i16; + let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 }; let imm31_12 = (val & 0xfffff000) as u32; let imm31_12_signed = imm31_12 as i32; From 547abd001b7b4900b55b54c55ac6c9417bcbbc4c Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Mon, 16 Jan 2023 19:12:20 +0100 Subject: [PATCH 042/128] Update some println to panic, fix RISCV_OP_M_MULH (line 270), add write_memory structure --- src/simulator/machine.rs | 57 +++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index a8084eb..672db4e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -63,6 +63,19 @@ impl Machine { ret } + /// Write to the main memory of the machine + /// + /// **machine** contains the memory + /// **size** the number of bytes to write (1, 2, 4 or 8) + /// **address** the address to write to + /// **value** data to be written + pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: i64) { + if ![1, 2, 3, 4].contains(&size) { + panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size) + } + todo!("Write memory not implemented yet"); + } + /// Execute the instructions table of a machine putted in param /// /// ### Parameters @@ -154,7 +167,7 @@ impl Machine { } }, _ => { - println!("In BR switch case, this should never happen... Instr was {}", inst.value); + panic!("In BR switch case, this should never happen... Instr was {}", inst.value); } } }, @@ -187,13 +200,31 @@ impl Machine { machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; }, _ => { - println!("In LD switch case, this should never happen... Instr was {}", inst.value); + panic!("In LD switch case, this should never happen... Instr was {}", inst.value); } } }, //TODO store instructions - + RISCV_ST => { + match inst.funct3 { + RISCV_ST_STB => { + todo!("Write memory here"); + }, + RISCV_ST_STH => { + todo!("Write memory here"); + }, + RISCV_ST_STW => { + todo!("Write memory here"); + }, + RISCV_ST_STD => { + todo!("Write memory here"); + }, + _ => { + panic!("In ST switch case, this should never happen... Instr was {}", inst.value); + } + } + } //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { @@ -223,12 +254,12 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; } } - _ => { println!("{} inconnu", inst.funct3); } + _ => { panic!("{} inconnu", inst.funct3); } } }, RISCV_OP => { - if inst.funct7 == 1{ + if inst.funct7 == 1 { match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; @@ -236,12 +267,12 @@ impl Machine { }, RISCV_OP_M_MULH => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; }, RISCV_OP_M_MULHSU => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; - long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -258,7 +289,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; } _ => { - println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); + panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); } } } else { @@ -303,7 +334,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; }, _ => { - println!("RISCV_OP undefined case\n"); + panic!("RISCV_OP undefined case\n"); } }//LA } @@ -335,7 +366,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned; }, _ => { - println!("this instruction ({}) doesn't exists", inst.value); + panic!("this instruction ({}) doesn't exists", inst.value); } } } else { @@ -362,12 +393,12 @@ impl Machine { } }, _ => { - println!("this instruction ({}) doesn't exists", inst.value); + panic!("this instruction ({}) doesn't exists", inst.value); } } } } - _ => { println!("{} opcode non géré", inst.opcode)}, + _ => { panic!("{} opcode non géré", inst.opcode)}, } machine.pc += 4; From 89cc9423bd7afb42a624fa796e29ab012fdc9714 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 15:03:58 +0100 Subject: [PATCH 043/128] Fix read_memory and implemented write_memory --- src/simulator/machine.rs | 41 +++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 672db4e..a94492d 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -37,43 +37,45 @@ impl Machine { /// Read from main memory of the machine /// + /// `panic!` when size is not 1, 2, 4 or 8 + /// /// ### Parameters /// /// - **machine** which contains the main memory /// - **size** the number of bytes to read (1, 2, 4, 8) /// - **address** in the memory to read pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { - if size != 1 && size != 2 && size != 4 && size != 8 { + if ![1, 2, 4, 8].contains(&size) { panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); } - let mut ret : u64 = machine.main_memory[address] as u64; - if size == 2 || size == 4 || size == 8 { + let mut ret: u64 = 0; + for i in 0..size { ret <<= 8; - ret += machine.main_memory[address + 1] as u64; - } - if size == 4 || size == 8 { - ret <<= 8; - ret += machine.main_memory[address + 2] as u64; - } - if size == 8 { - ret <<= 8; - ret += machine.main_memory[address + 3] as u64; + ret += machine.main_memory[address + i as usize] as u64; } ret } /// Write to the main memory of the machine /// - /// **machine** contains the memory - /// **size** the number of bytes to write (1, 2, 4 or 8) - /// **address** the address to write to - /// **value** data to be written - pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: i64) { - if ![1, 2, 3, 4].contains(&size) { + /// `panic!` when size is not 1, 2, 4 or 8 + /// + /// ### Parameters + /// + /// - **machine** contains the memory + /// - **size** the number of bytes to write (1, 2, 4 or 8) + /// - **address** the address to write to + /// - **value** data to be written + pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) { + if ![1, 2, 4, 8].contains(&size) { panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size) } - todo!("Write memory not implemented yet"); + let map: [u64; 8] = [0xff000000_00000000, 0x00ff0000_00000000, 0x0000ff00_00000000, 0x000000ff_00000000, + 0x00000000_ff00000000, 0x00000000_00ff0000, 0x00000000_0000ff00, 0x00000000_000000ff]; + for i in 0..size as usize { + machine.main_memory[address + i as usize] = (value & map[i]) as u8; + } } /// Execute the instructions table of a machine putted in param @@ -209,6 +211,7 @@ impl Machine { RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { + todo!("Write memory here"); }, RISCV_ST_STH => { From 1701e9b7d51f7c24c487ef19cc6fa9ee85e3841a Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 15:12:25 +0100 Subject: [PATCH 044/128] Fix RISCV_LD instructions --- src/simulator/machine.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index a94492d..73fc9f3 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -179,27 +179,27 @@ impl Machine { RISCV_LD => { match inst.funct3 { RISCV_LD_LB => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, RISCV_LD_LH => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, RISCV_LD_LW => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, RISCV_LD_LD => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, // same thing three opration ? RISCV_LD_LBU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, RISCV_LD_LHU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, RISCV_LD_LWU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; + machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); @@ -211,7 +211,7 @@ impl Machine { RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { - + todo!("Write memory here"); }, RISCV_ST_STH => { From b75c7b2d96fe824a2026916bf047e63034e33896 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 15:26:44 +0100 Subject: [PATCH 045/128] Add support for RISCV_ST instructions --- src/simulator/machine.rs | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 73fc9f3..000a1fe 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -211,17 +211,16 @@ impl Machine { RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { - - todo!("Write memory here"); + Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici }, RISCV_ST_STH => { - todo!("Write memory here"); + Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); }, RISCV_ST_STW => { - todo!("Write memory here"); + Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); }, RISCV_ST_STD => { - todo!("Write memory here"); + Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); }, _ => { panic!("In ST switch case, this should never happen... Instr was {}", inst.value); @@ -257,7 +256,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; } } - _ => { panic!("{} inconnu", inst.funct3); } + _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } } }, From 66eeb8f2b7975415b3448d9dab3aa9a3cca94570 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 17:01:48 +0100 Subject: [PATCH 046/128] Add tests momery --- src/simulator/machine.rs | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 000a1fe..e71328b 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -308,9 +308,9 @@ impl Machine { }, RISCV_OP_SLT => { if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { - machine.int_reg[inst.rd as usize] = 1; + machine.int_reg[inst.rd as usize] = 1; } else { - machine.int_reg[inst.rd as usize] = 0; + machine.int_reg[inst.rd as usize] = 0; } }, RISCV_OP_SLTU => { @@ -410,5 +410,20 @@ impl Machine { #[cfg(test)] mod test { + use crate::simulator::machine::Machine; + #[test] + fn test_read_memory() { + let mut m = Machine::_init_machine(); + m.main_memory[4] = 43; + m.main_memory[5] = 150; + assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); + } + + fn test_write_memory() { + let mut m = Machine::_init_machine(); + Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); + assert_eq!(43, m.main_memory[6]); + assert_eq!(150, m.main_memory[7]); + } } From 559f94ca210e6d5d2835a58e3b67f9802c54e78b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 17:42:56 +0100 Subject: [PATCH 047/128] Fi write_memory --- src/simulator/machine.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e71328b..0aab638 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -71,10 +71,9 @@ impl Machine { if ![1, 2, 4, 8].contains(&size) { panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size) } - let map: [u64; 8] = [0xff000000_00000000, 0x00ff0000_00000000, 0x0000ff00_00000000, 0x000000ff_00000000, - 0x00000000_ff00000000, 0x00000000_00ff0000, 0x00000000_0000ff00, 0x00000000_000000ff]; for i in 0..size as usize { - machine.main_memory[address + i as usize] = (value & map[i]) as u8; + let inv_i = size as usize - i - 1; + machine.main_memory[address + i as usize] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8; } } @@ -420,6 +419,7 @@ impl Machine { assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); } + #[test] fn test_write_memory() { let mut m = Machine::_init_machine(); Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); From f7f66d31e024533d82c50df316cd306f6feffb04 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 18 Jan 2023 22:15:06 +0100 Subject: [PATCH 048/128] Add a lot of comments, fix SRLI instruction in print, --- src/simulator/decode.rs | 2 +- src/simulator/machine.rs | 2 +- src/simulator/print.rs | 182 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 182 insertions(+), 4 deletions(-) diff --git a/src/simulator/decode.rs b/src/simulator/decode.rs index 91c8651..b388eb4 100644 --- a/src/simulator/decode.rs +++ b/src/simulator/decode.rs @@ -13,7 +13,7 @@ pub struct Instruction { pub funct7 : u8, pub funct7_smaller : u8, pub funct3 : u8, - pub shamt : u8, + pub shamt : u8, // shamt = imm[5:0] or imm[4:0] (depend of opcode) pub imm12_I : u16, pub imm12_S : u16, diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 0aab638..d191b74 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -206,7 +206,7 @@ impl Machine { } }, - //TODO store instructions + // store instructions RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 47cb58a..2e37d7a 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -2,12 +2,34 @@ #![allow(unused_variables)] use super::decode::{Instruction}; +// Instructions type: +// - R: Register / register +// - I: Immediate +// - U: Upper-Immediate +// - S: Store +// - B: Branch (conditional branches...) +// - J: Jump +/// Type: U +/// +/// Load upper immediate +/// +/// `LUI rd, imm31_12` => `rd <- imm31_12 << 12` +/// pub const RISCV_LUI: u8 = 0x37; +/// Type: U +/// +/// Add upper immediate to PC +/// +/// `AUIP rd, imm31_12` => `rd <- PC + imm31_12 << 12` pub const RISCV_AUIPC: u8 = 0x17; pub const RISCV_JAL: u8 = 0x6f; pub const RISCV_JALR: u8 = 0x67; pub const RISCV_BR: u8 = 0x63; + +/// Load instruction +/// +/// See func3 to know the type of instruction (LD, LW, LH, LB, LWU, LHU, LBU) pub const RISCV_LD: u8 = 0x3; pub const RISCV_ST: u8 = 0x23; pub const RISCV_OPI: u8 = 0x13; @@ -23,41 +45,197 @@ pub const RISCV_BR_BGE: u8 = 0x5; pub const RISCV_BR_BLTU: u8 = 0x6; pub const RISCV_BR_BGEU: u8 = 0x7; +/// Type: I +/// +/// Load byte (8 bits word) +/// +/// `LB rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LB: u8 = 0x0; +/// Type: I +/// +/// Load halfword (16 bits word) +/// +/// `LH rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LH: u8 = 0x1; +/// Type: I +/// +/// Load word (32 bits word) +/// +/// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LW: u8 = 0x2; +/// Type: I +/// +/// Load doubleword (64-bits word) +/// +/// `LD rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LD: u8 = 0x3; +/// Type: I +/// +/// Load byte unsigned +/// +/// `LBU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LBU: u8 = 0x4; +/// Type: I +/// +/// Load halfword unsigned +/// +/// `LHU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LHU: u8 = 0x5; +/// Type: I +/// +/// Load word unsigned (64 bits word) +/// +/// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` pub const RISCV_LD_LWU: u8 = 0x6; +/// Type: S +/// +/// Store halfword (SH) (16 bits) +/// +/// In case of overflow (rs2 is a 64 bits reg), only the first 16 bits values are stored +/// +/// `SH rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STH: u8 = 0x1; +/// Type: S +/// +/// Store word (SW) (32 bits) +/// +/// In case of overflow (rs2 is a 64 bits reg), only the first 32 bits values are stored +/// +/// `SW rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STW: u8 = 0x2; +/// Type: S +/// +/// Store byte (SB) (8 bits) +/// +/// In case of overflow (rs2 is a 64 bits reg), only the first 8 bits values are stored +/// +/// `SB rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STB: u8 = 0x0; +/// Type: S +/// +/// Store doubleword (SD) (64 bits) +/// +/// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STD: u8 = 0x3; +/// Type: I +/// +/// Add immediate +/// +/// `addi rd, rs1, imm12` => `rd <- rs1 + imm12` pub const RISCV_OPI_ADDI: u8 = 0x0; +/// Type: I +/// +/// Set less than immediate: set rd to 1 if rs1 < imm12, 0 otherwise +/// +/// `SLT rd, rs1, imm12` => `rd <- rs1 < imm12 ? 1 : 0` pub const RISCV_OPI_SLTI: u8 = 0x2; +/// Type: I +/// +/// Set less than immediate unsigned : same than SLTI but for unsigned values pub const RISCV_OPI_SLTIU: u8 = 0x3; +/// Type: I +/// +/// XOR immediate instruction +/// +/// `XORI rd, rs1, imm12` => `rd <- rs1 ^ imm12` pub const RISCV_OPI_XORI: u8 = 0x4; +/// Type: I +/// +/// OR immediate instruction +/// +/// `ORI rd, rs1, imm12` => `rd <- rs1 | imm12` pub const RISCV_OPI_ORI: u8 = 0x6; +/// Type: I +/// +/// AND immediate instruction +/// +/// `ANDI rd, rs1, imm12` => `rd <- rs1 & imm12` pub const RISCV_OPI_ANDI: u8 = 0x7; +/// Type: I +/// +/// Shift left logical immediate +/// +/// `SLLI rd, rs1, shamt` => `rd <- rs1 >> shamt` pub const RISCV_OPI_SLLI: u8 = 0x1; +/// Shift right immediate, may be SRAI or SRLI pub const RISCV_OPI_SRI: u8 = 0x5; +/// type: I +/// +/// Shift right arithmetic immediate +/// +/// `SRAI rd, rs1, shamt` => `rd <- rs1 >> shamt` pub const RISCV_OPI_SRI_SRAI: u8 = 0x20; +/// type: I +/// +/// Shift right logical immediate +/// +/// `SRLI rd, rs1, shamt` => `rd <- rs1 >> shamt` pub const RISCV_OPI_SRI_SRLI: u8 = 0x0; +/// Type: R +/// +/// Add or sub (see RISCV_OP_ADD_ADD or RISCV_OP_ADD_SUB) depending of func7 value pub const RISCV_OP_ADD: u8 = 0x0; +/// Type: R +/// +/// Shift left logical, add a 0 on right of the word +/// +/// `SLL rd, rs1, rs2` => `rs <- rs1 << rs2` pub const RISCV_OP_SLL: u8 = 0x1; +/// Type: R +/// +/// Set less than : set rd to 1 if rs1 < rs2, 0 otherwise +/// +/// `SLT rd, rs1, rs2` => `rd <- rs1 < rs2 ? 1 : 0` pub const RISCV_OP_SLT: u8 = 0x2; +/// Type: R +/// +/// Set less than unsigned : same than SLT but for unsigned values pub const RISCV_OP_SLTU: u8 = 0x3; +/// Type: R +/// +/// XOR instruction +/// +/// `XOR rd, rs1, rs2` => `rd <- rs1 ^ rs2` pub const RISCV_OP_XOR: u8 = 0x4; pub const RISCV_OP_SR: u8 = 0x5; +/// Type: R +/// +/// OR instruction +/// +/// `OR rd, rs1, rs2` => `rd <- rs1 | rs2` pub const RISCV_OP_OR: u8 = 0x6; +/// Type: R +/// +/// AND instruction +/// +/// `AND rd, rs1, rs2` => `rd <- rs1 & rs2` pub const RISCV_OP_AND: u8 = 0x7; +/// Type : R +/// +/// Addition +/// +/// `ADD rd, rs1, rs2` => `rd <- rs1 + rs2` pub const RISCV_OP_ADD_ADD: u8 = 0x0; +/// Type: R +/// +/// Substract +/// +/// `SUB rd, rs1, rs2` => `rd <- rs1 - rs2` pub const RISCV_OP_ADD_SUB: u8 = 0x20; +/// Type: R +/// +/// Shift right logical, add a 0 at the left of the word (should not used for signed values in most cases) +/// +/// `SRL rd, rs1, rs2` => `rd <- rs1 >> rs2` pub const RISCV_OP_SR_SRL: u8 = 0x0; +/// Type: R +/// +/// Shift right arithmetic, add a 1 at the left of the word(useful for signed values bacause it keep signed value) +/// +/// `SRA rd, rs1, rs2` => `rd <- rs1 >> rs2` pub const RISCV_OP_SR_SRA: u8 = 0x20; pub const RISCV_SYSTEM: u8 = 0x73; @@ -217,7 +395,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("slrii\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) + format!("srli\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } else { format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } @@ -295,7 +473,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_SYSTEM => { "ecall".to_string() }, - _ => "Unknown".to_string() // Error + _ => todo!("Unknown or currently unsupported opcode") // Change todo! to panic! in the future, I put todo! because there's a lot of opcode currently not implemented } } From 55f5726197d650b440e67f80a4a78dd566f3f0e7 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Fri, 20 Jan 2023 18:21:32 +0100 Subject: [PATCH 049/128] Move const to simulator/mod.rs --- src/simulator/machine.rs | 6 +- src/simulator/mod.rs | 527 ++++++++++++++++++++++++++++++++++++++- src/simulator/print.rs | 342 +------------------------ 3 files changed, 531 insertions(+), 344 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index d191b74..83be4a4 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -1,7 +1,7 @@ -use super::{decode::{Instruction, decode}, print::*}; - +use super::{decode::{Instruction, decode}}; +use super::global::*; /// doit disparaitre -const MEM_SIZE : usize= 4096; +const MEM_SIZE : usize = 4096; pub struct Machine { pub pc : u64, diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 581621e..3124579 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -1,3 +1,528 @@ pub mod machine; pub mod decode; -pub mod print; \ No newline at end of file +pub mod print; + + +pub mod global { + + #![allow(dead_code)] + #![allow(unused_variables)] + // Instructions type: + // - R: Register / register + // - I: Immediate + // - U: Upper-Immediate + // - S: Store + // - B: Branch (conditional branches...) + // - J: Jump + + // xlen = i64::MAX_VALUE on rv64 and i32::MAX_VALUE on rv32 + + /// Type: U + /// + /// Load upper immediate + /// + /// `LUI rd, imm31_12` => `rd <- imm31_12 << 12` + /// + pub const RISCV_LUI: u8 = 0x37; + /// Type: U + /// + /// Add upper immediate to PC + /// + /// `AUIP rd, imm31_12` => `rd <- PC + imm31_12 << 12` + pub const RISCV_AUIPC: u8 = 0x17; + /// Type: J + /// + /// Jump and link + /// + /// `JAL rd, imm20(rs1)` => `rd <- pc + 4; pc <- rs1 + imm12` + pub const RISCV_JAL: u8 = 0x6f; + /// type: J + /// + /// Jump and link register + /// + /// `JALR rd, imm12(rs1)` => `rd <- pc + 4; pc <- rs1 + imm12` + pub const RISCV_JALR: u8 = 0x67; + pub const RISCV_BR: u8 = 0x63; + + /// Load instructions + /// + /// See func3 to know the type of instruction (LD, LW, LH, LB, LWU, LHU, LBU) + pub const RISCV_LD: u8 = 0x3; + // Store instructions + pub const RISCV_ST: u8 = 0x23; + // immediate Arithmetic operations + pub const RISCV_OPI: u8 = 0x13; + // Arithmetic operations + pub const RISCV_OP: u8 = 0x33; + /// Immediate arithmetic operations for rv64i + pub const RISCV_OPIW: u8 = 0x1b; + // Arithmetic operations for rv64i + pub const RISCV_OPW: u8 = 0x3b; + + /// Type: B + /// + /// Branch equal + /// + /// `BEQ rs1, rs2, imm12` => `if rs1 = rs2 then pc <- pc + imm12` + pub const RISCV_BR_BEQ: u8 = 0x0; + /// Type: B + /// + /// Branch not equal + /// + /// `BNE rs1, rs2, imm12` => `if rs1 != rs2 then pc <- pc + imm12` + pub const RISCV_BR_BNE: u8 = 0x1; + /// Type: B + /// + /// Branch less than + /// + /// `BLT rs1, rs2, imm12` => `if rs1 < rs2 then pc <- pc + imm12` + pub const RISCV_BR_BLT: u8 = 0x4; + /// Type: B + /// + /// Branch greater than or equal + /// + /// `BGE rs1, rs2, imm12` => `if rs1 >= rs2 then pc <- pc + imm12` + pub const RISCV_BR_BGE: u8 = 0x5; + /// Type: B + /// + /// Branch less than unsigned + /// + /// Same as BLT but for unsigned values + pub const RISCV_BR_BLTU: u8 = 0x6; + /// Type: B + /// + /// Greater than or equal unsigned + /// + /// Same as BGE but for unsigned values + pub const RISCV_BR_BGEU: u8 = 0x7; + + /// Type: I + /// + /// Load byte (8 bits word) + /// + /// `LB rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LB: u8 = 0x0; + /// Type: I + /// + /// Load halfword (16 bits word) + /// + /// `LH rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LH: u8 = 0x1; + /// Type: I + /// + /// Load word (32 bits word) + /// + /// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LW: u8 = 0x2; + /// Type: I + /// + /// Load doubleword (64-bits word) + /// + /// `LD rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LD: u8 = 0x3; + /// Type: I + /// + /// Load byte unsigned + /// + /// `LBU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LBU: u8 = 0x4; + /// Type: I + /// + /// Load halfword unsigned + /// + /// `LHU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LHU: u8 = 0x5; + /// Type: I + /// + /// Load word unsigned (64 bits word) + /// + /// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` + pub const RISCV_LD_LWU: u8 = 0x6; + + /// Type: S + /// + /// Store halfword (SH) (16 bits) + /// + /// In case of overflow (rs2 is a 64 bits reg), only the first 16 bits values are stored + /// + /// `SH rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` + pub const RISCV_ST_STH: u8 = 0x1; + /// Type: S + /// + /// Store word (SW) (32 bits) + /// + /// In case of overflow (rs2 is a 64 bits reg), only the first 32 bits values are stored + /// + /// `SW rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` + pub const RISCV_ST_STW: u8 = 0x2; + /// Type: S + /// + /// Store byte (SB) (8 bits) + /// + /// In case of overflow (rs2 is a 64 bits reg), only the first 8 bits values are stored + /// + /// `SB rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` + pub const RISCV_ST_STB: u8 = 0x0; + /// Type: S + /// + /// Store doubleword (SD) (64 bits) + /// + /// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` + pub const RISCV_ST_STD: u8 = 0x3; + + /// Type: I + /// + /// Add immediate + /// + /// `addi rd, rs1, imm12` => `rd <- rs1 + imm12` + pub const RISCV_OPI_ADDI: u8 = 0x0; + /// Type: I + /// + /// Set less than immediate: set rd to 1 if rs1 < imm12, 0 otherwise + /// + /// `SLT rd, rs1, imm12` => `rd <- rs1 < imm12 ? 1 : 0` + pub const RISCV_OPI_SLTI: u8 = 0x2; + /// Type: I + /// + /// Set less than immediate unsigned : same than SLTI but for unsigned values + pub const RISCV_OPI_SLTIU: u8 = 0x3; + /// Type: I + /// + /// XOR immediate instruction + /// + /// `XORI rd, rs1, imm12` => `rd <- rs1 ^ imm12` + pub const RISCV_OPI_XORI: u8 = 0x4; + /// Type: I + /// + /// OR immediate instruction + /// + /// `ORI rd, rs1, imm12` => `rd <- rs1 | imm12` + pub const RISCV_OPI_ORI: u8 = 0x6; + /// Type: I + /// + /// AND immediate instruction + /// + /// `ANDI rd, rs1, imm12` => `rd <- rs1 & imm12` + pub const RISCV_OPI_ANDI: u8 = 0x7; + /// Type: I + /// + /// Shift left logical immediate + /// + /// `SLLI rd, rs1, shamt` => `rd <- rs1 >> shamt` + pub const RISCV_OPI_SLLI: u8 = 0x1; + /// Shift right immediate, may be SRAI or SRLI + pub const RISCV_OPI_SRI: u8 = 0x5; + /// type: I + /// + /// Shift right arithmetic immediate + /// + /// `SRAI rd, rs1, shamt` => `rd <- rs1 >> shamt` + pub const RISCV_OPI_SRI_SRAI: u8 = 0x20; + /// type: I + /// + /// Shift right logical immediate + /// + /// `SRLI rd, rs1, shamt` => `rd <- rs1 >> shamt` + pub const RISCV_OPI_SRI_SRLI: u8 = 0x0; + + /// Type: R + /// + /// Add or sub (see RISCV_OP_ADD_ADD or RISCV_OP_ADD_SUB) depending of func7 value + pub const RISCV_OP_ADD: u8 = 0x0; + /// Type: R + /// + /// Shift left logical, add a 0 on right of the word + /// + /// `SLL rd, rs1, rs2` => `rs <- rs1 << rs2` + pub const RISCV_OP_SLL: u8 = 0x1; + /// Type: R + /// + /// Set less than : set rd to 1 if rs1 < rs2, 0 otherwise + /// + /// `SLT rd, rs1, rs2` => `rd <- rs1 < rs2 ? 1 : 0` + pub const RISCV_OP_SLT: u8 = 0x2; + /// Type: R + /// + /// Set less than unsigned : same than SLT but for unsigned values + pub const RISCV_OP_SLTU: u8 = 0x3; + /// Type: R + /// + /// XOR instruction + /// + /// `XOR rd, rs1, rs2` => `rd <- rs1 ^ rs2` + pub const RISCV_OP_XOR: u8 = 0x4; + pub const RISCV_OP_SR: u8 = 0x5; + /// Type: R + /// + /// OR instruction + /// + /// `OR rd, rs1, rs2` => `rd <- rs1 | rs2` + pub const RISCV_OP_OR: u8 = 0x6; + /// Type: R + /// + /// AND instruction + /// + /// `AND rd, rs1, rs2` => `rd <- rs1 & rs2` + pub const RISCV_OP_AND: u8 = 0x7; + /// Type : R + /// + /// Addition + /// + /// `ADD rd, rs1, rs2` => `rd <- rs1 + rs2` + pub const RISCV_OP_ADD_ADD: u8 = 0x0; + /// Type: R + /// + /// Substract + /// + /// `SUB rd, rs1, rs2` => `rd <- rs1 - rs2` + pub const RISCV_OP_ADD_SUB: u8 = 0x20; + /// Type: R + /// + /// Shift right logical, add a 0 at the left of the word (should not used for signed values in most cases) + /// + /// `SRL rd, rs1, rs2` => `rd <- rs1 >> rs2` + pub const RISCV_OP_SR_SRL: u8 = 0x0; + /// Type: R + /// + /// Shift right arithmetic, add a 1 at the left of the word(useful for signed values bacause it keep signed value) + /// + /// `SRA rd, rs1, rs2` => `rd <- rs1 >> rs2` + pub const RISCV_OP_SR_SRA: u8 = 0x20; + + // ECALL or EBREAK from base instructions + /// or instructions from Ricsr extension + pub const RISCV_SYSTEM: u8 = 0x73; + + /// Type: I + /// + /// Add immediate word (RV64I only) + /// + /// `ADDIW rd, rs1, imm12` => `rd <- rs1 + imm12` + pub const RISCV_OPIW_ADDIW: u8 = 0x0; + /// Type: I + /// + /// Shift right logical immediate word (RV64I only) + /// + /// `SLLIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + pub const RISCV_OPIW_SLLIW: u8 = 0x1; + + /// Shift right immediate instructions (logical or arithmetic depend of func7) + pub const RISCV_OPIW_SRW: u8 = 0x5; + /// Type: I + /// + /// Shift right logical immediate word (RV64I only) + /// + /// `SRLIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + /// + /// Complete left bits by a zero, should be used with an unsigned value in most case + pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; + /// Type: I + /// + /// Shift right arithmetic immediate word (RV64I only) + /// + /// `SRAIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + /// + /// Keep sign bit + pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; + + // ADD or SUB immediate instructions, depend of func7 value + pub const RISCV_OPW_ADDSUBW: u8 = 0x0; + /// Type: R + /// + /// Shift left logical word (RV64I only) + /// + /// `SLLW rd, rs1, rs2` => `rd <- rs1 << rs2` + pub const RISCV_OPW_SLLW: u8 = 0x1; + /// Shift right word instructions (logical or arithmetic depend of func3) + pub const RISCV_OPW_SRW: u8 = 0x5; + /// Type: R + /// + /// Add word (rv64I only) + /// + /// `ADDW rd, rs1, rs2` => `rd <- rs1 + rs2` + pub const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; + /// Type: R + /// + /// Subtract word (rv64I only) + /// + /// `SUBW rd, rs1, rs2` => `rd <- rs1 - rs2` + pub const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; + /// Type: R + /// + /// Shift right logical word (rv64I only) + /// + /// rd <- rs1 >> rs2 + /// + /// Complete left bits by a 0, should be used with an unsigned value + pub const RISCV_OPW_SRW_SRLW: u8 = 0x0; + /// Type: R + /// + /// Shift right arithmetic word (rv64I only) + /// + /// `SRAW rd, rs1, rs2` => `rd <- rs1 >> rs2` + /// + /// Keep sign bit + pub const RISCV_OPW_SRW_SRAW: u8 = 0x20; + + pub const RISCV_SYSTEM_ENV: u8 = 0x0; + pub const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; + pub const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; + pub const RISCV_SYSTEM_CSRRS: u8 = 0x2; + pub const RISCV_SYSTEM_CSRRW: u8 = 0x1; + pub const RISCV_SYSTEM_CSRRC: u8 = 0x3; + pub const RISCV_SYSTEM_CSRRWI: u8 = 0x5; + pub const RISCV_SYSTEM_CSRRSI: u8 = 0x6; + pub const RISCV_SYSTEM_CSRRCI: u8 = 0x7; + + pub const RISCV_FLW: u8 = 0x07; + pub const RISCV_FSW: u8 = 0x27; + pub const RISCV_FMADD: u8 = 0x43; + pub const RISCV_FMSUB: u8 = 0x47; + pub const RISCV_FNMSUB: u8 = 0x4b; + pub const RISCV_FNMADD: u8 = 0x4f; + /// Simple floating point extension + pub const RISCV_FP: u8 = 0x53; + + pub const RISCV_FP_ADD: u8 = 0x0; + pub const RISCV_FP_SUB: u8 = 0x4; + pub const RISCV_FP_MUL: u8 = 0x8; + pub const RISCV_FP_DIV: u8 = 0xc; + pub const RISCV_FP_SQRT: u8 = 0x2c; + pub const RISCV_FP_FSGN: u8 = 0x10; + pub const RISCV_FP_MINMAX: u8 = 0x14; + pub const RISCV_FP_FCVTW: u8 = 0x60; + pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; + pub const RISCV_FP_FCMP: u8 = 0x50; + pub const RISCV_FP_FEQS: u8 = 0x53; + pub const RISCV_FP_FCVTS: u8 = 0x68; + pub const RISCV_FP_FCVTDS: u8 = 0x21; + + pub const RISCV_FP_FSGN_J: u8 = 0x0; + pub const RISCV_FP_FSGN_JN: u8 = 0x1; + pub const RISCV_FP_FSGN_JX: u8 = 0x2; + + pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; + pub const RISCV_FP_MINMAX_MAX: u8 = 0x1; + + pub const RISCV_FP_FCVTW_W: u8 = 0x0; + pub const RISCV_FP_FCVTW_WU: u8 = 0x1; + + pub const RISCV_FP_FCVTS_W: u8 = 0x0; + pub const RISCV_FP_FCVTS_WU: u8 = 0x1; + + pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; + pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; + + pub const RISCV_FP_FCMP_FEQ: u8 = 2; + pub const RISCV_FP_FCMP_FLT: u8 = 1; + pub const RISCV_FP_FCMP_FLE: u8 = 0; + + pub const RISCV_FP_FMVW: u8 = 0x78; + + /// Integer, multiplication and division extension + pub const RISCV_OP_M: u8 = 0x1; + + /// Type: R + /// + /// Multiply + /// + /// `MUL rd, rs1, rs2` => `rd <- rs1 * rs2` + pub const RISCV_OP_M_MUL: u8 = 0x0; + /// Type: R + /// + /// Multiply high signed signed + /// + /// `MULH rd, rs1, rs2` => `rd <- (rs1 * rs2) >> xlen` + /// + /// rs1 and rs2 signed + pub const RISCV_OP_M_MULH: u8 = 0x1; + /// Type: R + /// + /// Multiply high signed unsigned + /// + /// `MULHSU rd, rs1, rs2` => `rd <- (rs1 x rs2) >> xlen` + /// + /// rs1 is signed and rs2 is unsigned + pub const RISCV_OP_M_MULHSU: u8 = 0x2; + /// Type: R + /// + /// Multiply high unsigned unsigned + /// + /// `MULHU rd, rs1, rs2` => `rd <- (rs1 × rs2) >> xlen` + /// + /// rs1 and rs2 unsigned + pub const RISCV_OP_M_MULHU: u8 = 0x3; + /// Type: R + /// + /// Divide signed + /// + /// `DIV rd, rs1, rs2` => `rd <- r1 / rs2` + pub const RISCV_OP_M_DIV: u8 = 0x4; + /// Type: R + /// + /// Divide unsigned + /// + /// `DIVU rd, rs1, rs2` => `rd <- rs1 / rs2` + pub const RISCV_OP_M_DIVU: u8 = 0x5; + /// Type: R + /// + /// Remainder signed + /// + /// `REM rd, rs1, rs2` => `rd <- rs1 % rs2` + pub const RISCV_OP_M_REM: u8 = 0x6; + /// Type: R + /// + /// Remaindder unsigned + /// + /// `REMU rd, rs1, rs2` => `rd <- rs1 % rs2` + pub const RISCV_OP_M_REMU: u8 = 0x7; + + /// Type: R + /// + /// Multiply Word (rv64M only) + /// + /// `MULW rd, rs1, rs2` => `rd <- rs1 * rs2` + pub const RISCV_OPW_M_MULW: u8 = 0x0; + /// Type: R + /// + /// Divide signed word (RV64M only) + /// + /// `DIVW rd, rs1, rs2` => `rd <- rs1 / rs2` + pub const RISCV_OPW_M_DIVW: u8 = 0x4; + /// Type: R + /// + /// Divide unsigned word + /// + /// `DIVUW rd, rs1, rs2` => `red <- rs1 / rs2` + pub const RISCV_OPW_M_DIVUW: u8 = 0x5; + /// Type: R + /// + /// Remainder signed word (RV64M only) + /// + /// `REMW rd, rs1, rs2` => `rd <- rs1 % rs2` + pub const RISCV_OPW_M_REMW: u8 = 0x6; + /// Type: R + /// + /// Remainder unsigned word (RV64M only) + /// + /// `REMUW rd, rs1, rs2` => `rd <- rs1 % rs2` + pub const RISCV_OPW_M_REMUW: u8 = 0x7; + + /// Instruction from Zifencei extension + pub const RISCV_FENCE: u8 = 0x0f; + + /// Atomic instructions extension + pub const RISCV_ATOM: u8 = 0x2f; + pub const RISCV_ATOM_LR: u8 = 0x2; + pub const RISCV_ATOM_SC: u8 = 0x3; + pub const RISCV_ATOM_SWAP: u8 = 0x1; + pub const RISCV_ATOM_ADD: u8 = 0; + pub const RISCV_ATOM_XOR: u8 = 0x4; + pub const RISCV_ATOM_AND: u8 = 0xc; + pub const RISCV_ATOM_OR: u8 = 0x8; + pub const RISCV_ATOM_MIN: u8 = 0x10; + pub const RISCV_ATOM_MAX: u8 = 0x14; + pub const RISCV_ATOM_MINU: u8 = 0x18; + pub const RISCV_ATOM_MAXU: u8 = 0x1c; + +} \ No newline at end of file diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 2e37d7a..8544334 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -1,345 +1,7 @@ #![allow(dead_code)] #![allow(unused_variables)] use super::decode::{Instruction}; - -// Instructions type: -// - R: Register / register -// - I: Immediate -// - U: Upper-Immediate -// - S: Store -// - B: Branch (conditional branches...) -// - J: Jump - -/// Type: U -/// -/// Load upper immediate -/// -/// `LUI rd, imm31_12` => `rd <- imm31_12 << 12` -/// -pub const RISCV_LUI: u8 = 0x37; -/// Type: U -/// -/// Add upper immediate to PC -/// -/// `AUIP rd, imm31_12` => `rd <- PC + imm31_12 << 12` -pub const RISCV_AUIPC: u8 = 0x17; -pub const RISCV_JAL: u8 = 0x6f; -pub const RISCV_JALR: u8 = 0x67; -pub const RISCV_BR: u8 = 0x63; - -/// Load instruction -/// -/// See func3 to know the type of instruction (LD, LW, LH, LB, LWU, LHU, LBU) -pub const RISCV_LD: u8 = 0x3; -pub const RISCV_ST: u8 = 0x23; -pub const RISCV_OPI: u8 = 0x13; -pub const RISCV_OP: u8 = 0x33; -pub const RISCV_OPIW: u8 = 0x1b; -pub const RISCV_OPW: u8 = 0x3b; - - -pub const RISCV_BR_BEQ: u8 = 0x0; -pub const RISCV_BR_BNE: u8 = 0x1; -pub const RISCV_BR_BLT: u8 = 0x4; -pub const RISCV_BR_BGE: u8 = 0x5; -pub const RISCV_BR_BLTU: u8 = 0x6; -pub const RISCV_BR_BGEU: u8 = 0x7; - -/// Type: I -/// -/// Load byte (8 bits word) -/// -/// `LB rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LB: u8 = 0x0; -/// Type: I -/// -/// Load halfword (16 bits word) -/// -/// `LH rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LH: u8 = 0x1; -/// Type: I -/// -/// Load word (32 bits word) -/// -/// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LW: u8 = 0x2; -/// Type: I -/// -/// Load doubleword (64-bits word) -/// -/// `LD rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LD: u8 = 0x3; -/// Type: I -/// -/// Load byte unsigned -/// -/// `LBU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LBU: u8 = 0x4; -/// Type: I -/// -/// Load halfword unsigned -/// -/// `LHU rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LHU: u8 = 0x5; -/// Type: I -/// -/// Load word unsigned (64 bits word) -/// -/// `LW rd, imm12(rs1)` => `rd <- mem[rs1 + imm12]` -pub const RISCV_LD_LWU: u8 = 0x6; - -/// Type: S -/// -/// Store halfword (SH) (16 bits) -/// -/// In case of overflow (rs2 is a 64 bits reg), only the first 16 bits values are stored -/// -/// `SH rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` -pub const RISCV_ST_STH: u8 = 0x1; -/// Type: S -/// -/// Store word (SW) (32 bits) -/// -/// In case of overflow (rs2 is a 64 bits reg), only the first 32 bits values are stored -/// -/// `SW rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` -pub const RISCV_ST_STW: u8 = 0x2; -/// Type: S -/// -/// Store byte (SB) (8 bits) -/// -/// In case of overflow (rs2 is a 64 bits reg), only the first 8 bits values are stored -/// -/// `SB rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` -pub const RISCV_ST_STB: u8 = 0x0; -/// Type: S -/// -/// Store doubleword (SD) (64 bits) -/// -/// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` -pub const RISCV_ST_STD: u8 = 0x3; - -/// Type: I -/// -/// Add immediate -/// -/// `addi rd, rs1, imm12` => `rd <- rs1 + imm12` -pub const RISCV_OPI_ADDI: u8 = 0x0; -/// Type: I -/// -/// Set less than immediate: set rd to 1 if rs1 < imm12, 0 otherwise -/// -/// `SLT rd, rs1, imm12` => `rd <- rs1 < imm12 ? 1 : 0` -pub const RISCV_OPI_SLTI: u8 = 0x2; -/// Type: I -/// -/// Set less than immediate unsigned : same than SLTI but for unsigned values -pub const RISCV_OPI_SLTIU: u8 = 0x3; -/// Type: I -/// -/// XOR immediate instruction -/// -/// `XORI rd, rs1, imm12` => `rd <- rs1 ^ imm12` -pub const RISCV_OPI_XORI: u8 = 0x4; -/// Type: I -/// -/// OR immediate instruction -/// -/// `ORI rd, rs1, imm12` => `rd <- rs1 | imm12` -pub const RISCV_OPI_ORI: u8 = 0x6; -/// Type: I -/// -/// AND immediate instruction -/// -/// `ANDI rd, rs1, imm12` => `rd <- rs1 & imm12` -pub const RISCV_OPI_ANDI: u8 = 0x7; -/// Type: I -/// -/// Shift left logical immediate -/// -/// `SLLI rd, rs1, shamt` => `rd <- rs1 >> shamt` -pub const RISCV_OPI_SLLI: u8 = 0x1; -/// Shift right immediate, may be SRAI or SRLI -pub const RISCV_OPI_SRI: u8 = 0x5; -/// type: I -/// -/// Shift right arithmetic immediate -/// -/// `SRAI rd, rs1, shamt` => `rd <- rs1 >> shamt` -pub const RISCV_OPI_SRI_SRAI: u8 = 0x20; -/// type: I -/// -/// Shift right logical immediate -/// -/// `SRLI rd, rs1, shamt` => `rd <- rs1 >> shamt` -pub const RISCV_OPI_SRI_SRLI: u8 = 0x0; - -/// Type: R -/// -/// Add or sub (see RISCV_OP_ADD_ADD or RISCV_OP_ADD_SUB) depending of func7 value -pub const RISCV_OP_ADD: u8 = 0x0; -/// Type: R -/// -/// Shift left logical, add a 0 on right of the word -/// -/// `SLL rd, rs1, rs2` => `rs <- rs1 << rs2` -pub const RISCV_OP_SLL: u8 = 0x1; -/// Type: R -/// -/// Set less than : set rd to 1 if rs1 < rs2, 0 otherwise -/// -/// `SLT rd, rs1, rs2` => `rd <- rs1 < rs2 ? 1 : 0` -pub const RISCV_OP_SLT: u8 = 0x2; -/// Type: R -/// -/// Set less than unsigned : same than SLT but for unsigned values -pub const RISCV_OP_SLTU: u8 = 0x3; -/// Type: R -/// -/// XOR instruction -/// -/// `XOR rd, rs1, rs2` => `rd <- rs1 ^ rs2` -pub const RISCV_OP_XOR: u8 = 0x4; -pub const RISCV_OP_SR: u8 = 0x5; -/// Type: R -/// -/// OR instruction -/// -/// `OR rd, rs1, rs2` => `rd <- rs1 | rs2` -pub const RISCV_OP_OR: u8 = 0x6; -/// Type: R -/// -/// AND instruction -/// -/// `AND rd, rs1, rs2` => `rd <- rs1 & rs2` -pub const RISCV_OP_AND: u8 = 0x7; -/// Type : R -/// -/// Addition -/// -/// `ADD rd, rs1, rs2` => `rd <- rs1 + rs2` -pub const RISCV_OP_ADD_ADD: u8 = 0x0; -/// Type: R -/// -/// Substract -/// -/// `SUB rd, rs1, rs2` => `rd <- rs1 - rs2` -pub const RISCV_OP_ADD_SUB: u8 = 0x20; -/// Type: R -/// -/// Shift right logical, add a 0 at the left of the word (should not used for signed values in most cases) -/// -/// `SRL rd, rs1, rs2` => `rd <- rs1 >> rs2` -pub const RISCV_OP_SR_SRL: u8 = 0x0; -/// Type: R -/// -/// Shift right arithmetic, add a 1 at the left of the word(useful for signed values bacause it keep signed value) -/// -/// `SRA rd, rs1, rs2` => `rd <- rs1 >> rs2` -pub const RISCV_OP_SR_SRA: u8 = 0x20; - -pub const RISCV_SYSTEM: u8 = 0x73; - -pub const RISCV_OPIW_ADDIW: u8 = 0x0; -pub const RISCV_OPIW_SLLIW: u8 = 0x1; -pub const RISCV_OPIW_SRW: u8 = 0x5; -pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; -pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; - -pub const RISCV_OPW_ADDSUBW: u8 = 0x0; -pub const RISCV_OPW_SLLW: u8 = 0x1; -pub const RISCV_OPW_SRW: u8 = 0x5; -pub const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; -pub const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; -pub const RISCV_OPW_SRW_SRLW: u8 = 0x0; -pub const RISCV_OPW_SRW_SRAW: u8 = 0x20; - -pub const RISCV_SYSTEM_ENV: u8 = 0x0; -pub const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; -pub const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; -pub const RISCV_SYSTEM_CSRRS: u8 = 0x2; -pub const RISCV_SYSTEM_CSRRW: u8 = 0x1; -pub const RISCV_SYSTEM_CSRRC: u8 = 0x3; -pub const RISCV_SYSTEM_CSRRWI: u8 = 0x5; -pub const RISCV_SYSTEM_CSRRSI: u8 = 0x6; -pub const RISCV_SYSTEM_CSRRCI: u8 = 0x7; - -pub const RISCV_FLW: u8 = 0x07; -pub const RISCV_FSW: u8 = 0x27; -pub const RISCV_FMADD: u8 = 0x43; -pub const RISCV_FMSUB: u8 = 0x47; -pub const RISCV_FNMSUB: u8 = 0x4b; -pub const RISCV_FNMADD: u8 = 0x4f; -pub const RISCV_FP: u8 = 0x53; - -pub const RISCV_FP_ADD: u8 = 0x0; -pub const RISCV_FP_SUB: u8 = 0x4; -pub const RISCV_FP_MUL: u8 = 0x8; -pub const RISCV_FP_DIV: u8 = 0xc; -pub const RISCV_FP_SQRT: u8 = 0x2c; -pub const RISCV_FP_FSGN: u8 = 0x10; -pub const RISCV_FP_MINMAX: u8 = 0x14; -pub const RISCV_FP_FCVTW: u8 = 0x60; -pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; -pub const RISCV_FP_FCMP: u8 = 0x50; -pub const RISCV_FP_FEQS: u8 = 0x53; -pub const RISCV_FP_FCVTS: u8 = 0x68; -pub const RISCV_FP_FCVTDS: u8 = 0x21; - -pub const RISCV_FP_FSGN_J: u8 = 0x0; -pub const RISCV_FP_FSGN_JN: u8 = 0x1; -pub const RISCV_FP_FSGN_JX: u8 = 0x2; - -pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; -pub const RISCV_FP_MINMAX_MAX: u8 = 0x1; - -pub const RISCV_FP_FCVTW_W: u8 = 0x0; -pub const RISCV_FP_FCVTW_WU: u8 = 0x1; - -pub const RISCV_FP_FCVTS_W: u8 = 0x0; -pub const RISCV_FP_FCVTS_WU: u8 = 0x1; - -pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; -pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; - -pub const RISCV_FP_FCMP_FEQ: u8 = 2; -pub const RISCV_FP_FCMP_FLT: u8 = 1; -pub const RISCV_FP_FCMP_FLE: u8 = 0; - -pub const RISCV_FP_FMVW: u8 = 0x78; - -pub const RISCV_OP_M: u8 = 0x1; - -pub const RISCV_OP_M_MUL: u8 = 0x0; -pub const RISCV_OP_M_MULH: u8 = 0x1; -pub const RISCV_OP_M_MULHSU: u8 = 0x2; -pub const RISCV_OP_M_MULHU: u8 = 0x3; -pub const RISCV_OP_M_DIV: u8 = 0x4; -pub const RISCV_OP_M_DIVU: u8 = 0x5; -pub const RISCV_OP_M_REM: u8 = 0x6; -pub const RISCV_OP_M_REMU: u8 = 0x7; - -pub const RISCV_OPW_M_MULW: u8 = 0x0; -pub const RISCV_OPW_M_DIVW: u8 = 0x4; -pub const RISCV_OPW_M_DIVUW: u8 = 0x5; -pub const RISCV_OPW_M_REMW: u8 = 0x6; -pub const RISCV_OPW_M_REMUW: u8 = 0x7; - -pub const RISCV_FENCE: u8 = 0x0f; - -pub const RISCV_ATOM: u8 = 0x2f; -pub const RISCV_ATOM_LR: u8 = 0x2; -pub const RISCV_ATOM_SC: u8 = 0x3; -pub const RISCV_ATOM_SWAP: u8 = 0x1; -pub const RISCV_ATOM_ADD: u8 = 0; -pub const RISCV_ATOM_XOR: u8 = 0x4; -pub const RISCV_ATOM_AND: u8 = 0xc; -pub const RISCV_ATOM_OR: u8 = 0x8; -pub const RISCV_ATOM_MIN: u8 = 0x10; -pub const RISCV_ATOM_MAX: u8 = 0x14; -pub const RISCV_ATOM_MINU: u8 = 0x18; -pub const RISCV_ATOM_MAXU: u8 = 0x1c; - +use super::global::*; const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; @@ -481,8 +143,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] mod test { - #![allow(clippy::unusual_byte_groupings)] + use crate::simulator::{decode, print}; From 0c04f4bf6da879043bd90489d2ac78dea5154cd3 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Mon, 23 Jan 2023 12:52:32 +0100 Subject: [PATCH 050/128] All some fp instruction documentation --- src/simulator/mod.rs | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 3124579..9f3f208 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -380,15 +380,43 @@ pub mod global { pub const RISCV_FMSUB: u8 = 0x47; pub const RISCV_FNMSUB: u8 = 0x4b; pub const RISCV_FNMADD: u8 = 0x4f; + /// Simple floating point extension pub const RISCV_FP: u8 = 0x53; + /// Type: R + /// + /// Simple precision floating point addition + /// + /// `FADD.S rd, rs1, rs2` => `rd <- rs1 + rs2` pub const RISCV_FP_ADD: u8 = 0x0; + /// Type: R + /// + /// Simple precision floating point substraction + /// + /// `FSUB.S rd, rs1, rs2` => `rd <- rs1 - rs2` pub const RISCV_FP_SUB: u8 = 0x4; + /// Type: R + /// + /// Simple precision floating point multiplication + /// + /// `fmul.s rd, rs1, rs2` => `rd <- rs1 * rs2` pub const RISCV_FP_MUL: u8 = 0x8; + /// Type : R + /// + /// Simple precision floating point division + /// + /// `fdiv.s rd, rs1, rs2` => `rd <- rs1 / rs2` pub const RISCV_FP_DIV: u8 = 0xc; + /// Type: R + /// + /// Simple precision square root + /// + /// `fsqrt.s rd, rs1` => `rd <- sqrt(rs1)` pub const RISCV_FP_SQRT: u8 = 0x2c; + /// FSGN instructions pub const RISCV_FP_FSGN: u8 = 0x10; + // fmin or fmax instructions pub const RISCV_FP_MINMAX: u8 = 0x14; pub const RISCV_FP_FCVTW: u8 = 0x60; pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; @@ -397,8 +425,23 @@ pub mod global { pub const RISCV_FP_FCVTS: u8 = 0x68; pub const RISCV_FP_FCVTDS: u8 = 0x21; + /// Type: R + /// + /// Take all bits except sign bit from rs1. sign is rs2's sign bit + /// + /// `fsgnj.s rd, rs1, rs2` => `rd <- {rs2[31], rs1[30:0]}` pub const RISCV_FP_FSGN_J: u8 = 0x0; + /// Type: R + /// + /// Take all bits except sign bit from rs1, sign is opposite of rs2's sign bit + /// + /// `fsgnjs.s rd, rs1, rs2` => `rd <- {rs2[31], rs[30:0]}` pub const RISCV_FP_FSGN_JN: u8 = 0x1; + /// Type: R + /// + /// Take all bits except sign bit from rs1, sign is XOR of sign bit of rs1 and rs2 + /// + /// `fsgnjx.s rd, rs1, rs2` => `rd <- {rs1[31] ^ rs2[31], rs1[30:0]}` pub const RISCV_FP_FSGN_JX: u8 = 0x2; pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; From 40374bf26f5a9fc403fc57c47356e69980e6047b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Mon, 23 Jan 2023 14:29:37 +0100 Subject: [PATCH 051/128] F extension documentation done --- src/simulator/mod.rs | 91 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 9f3f208..6aef6be 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -418,10 +418,18 @@ pub mod global { pub const RISCV_FP_FSGN: u8 = 0x10; // fmin or fmax instructions pub const RISCV_FP_MINMAX: u8 = 0x14; + /// fcvt.w instructions + /// + /// convert fp to integer pub const RISCV_FP_FCVTW: u8 = 0x60; + /// fmv.x.w or fclass.s instruction pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; + /// floating points comparaison instructions pub const RISCV_FP_FCMP: u8 = 0x50; pub const RISCV_FP_FEQS: u8 = 0x53; + /// fcvt.s instructions + /// + /// Convert integer to fp pub const RISCV_FP_FCVTS: u8 = 0x68; pub const RISCV_FP_FCVTDS: u8 = 0x21; @@ -444,22 +452,101 @@ pub mod global { /// `fsgnjx.s rd, rs1, rs2` => `rd <- {rs1[31] ^ rs2[31], rs1[30:0]}` pub const RISCV_FP_FSGN_JX: u8 = 0x2; + /// Type: R + /// + /// write the smaller number between rs1 and rs2 to rd + /// + /// `fmin.s rd, rs1, rs2` => `rd <- min(rs1, rs2)` pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; + /// type: R + /// + /// Write the larger number between rs1 and rs2 to rd + /// + /// `fmax.s rd, rs1, rs2` => `rd <- max(rs1, rs2)` pub const RISCV_FP_MINMAX_MAX: u8 = 0x1; - + + /// Type: R + /// + /// Convert a floating point number in register to a signed 32-bit integer and write it in integer register + /// + /// `fcvt.w.s rd, rs1` => `rd <- rs1_f32 as i32` + /// + /// rd is integer register and rs1 is floating point register pub const RISCV_FP_FCVTW_W: u8 = 0x0; + /// Type: R + /// + /// Convert a floating point number in register to a unsigned 32 bit integer and write it in integer register + /// + /// `fcvt.wu.s rd, rs1` => `rd <- rs1_f32 as u32` pub const RISCV_FP_FCVTW_WU: u8 = 0x1; + /// Type : R + /// + /// Convert signed 32 bit integer in register to a floating point number and write it in fp register + /// + /// `fcvt.s.w rd, rs1` => `rd <- rs1_s32 as f32` pub const RISCV_FP_FCVTS_W: u8 = 0x0; + /// Type: R + /// + /// Convert unsigned 32 bit integer in register to a floating point number and write it in fp register + /// + /// `fcvt.s.wu rd, rs1` => `rd <- rs1_u32 as f32` pub const RISCV_FP_FCVTS_WU: u8 = 0x1; - + /// Type: R + /// + /// Move floating point value in register to integer register, bits value aren't modified during the process + /// + /// On rv64, the lower 32 bits of the integer register are transfered, for the upper 32 bits, values are filles with copies of the floating point number's sign bit + /// + /// `fmv.x.w rd ,rs1` => `rd[31,0] <- rs1; rd[63:32] <- rs[31]` pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; + /// Type: R + /// + /// examine the value given in fp register rs1 and writes to integer register rd a 10 bit mask that indicates the class of the fp number. + /// Format is described here: + /// + /// | rd bit | meaning | + /// |--------|------------------------------------| + /// | 0 | rs1 is -infinite | + /// | 1 | rs1 is a negative normal number | + /// | 2 | rs1 is a negative subnormal number | + /// | 3 | rs1 is -0 | + /// | 4 | rs1 is +0 | + /// | 5 | rs1 is a positive subnormal number | + /// | 6 | rs1 is a positive normal number | + /// | 7 | rs1 is +infinite | + /// | 8 | rs1 is a signaling NaN | + /// | 9 | rs1 is a quiet NaN | + /// + /// All others bit in rd are cleared pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; + /// Type: R + /// + /// Quiet equal comparaison, NaN cause an invalid operation exception + /// + /// `feq.s rd, rs1, rs2` => `rd <- rs1 == rs2` pub const RISCV_FP_FCMP_FEQ: u8 = 2; + /// Type: R + /// + /// Quiet less comparaison, NaN cause an invalid operation exception + /// + /// `flt.s rd, rs1, rs2` => `rdf <- rs1 < rs2` pub const RISCV_FP_FCMP_FLT: u8 = 1; + /// Type: R + /// + /// Quiet less or equal comparaison, NaN cause an invalid operation exception + /// + /// `fle.s rd, rs1, rs2` => `rd <- rs1 <= rs2` pub const RISCV_FP_FCMP_FLE: u8 = 0; + /// Type : R + /// + /// Move floating point value in integer register to the fp register. Bits aren't modified in the transfer + /// + /// On rv64, only the lower 32 bits in the integer register are transfered. + /// + /// `fmv.w.x rd, rs1` => `rd <- rs1[31:0]` pub const RISCV_FP_FMVW: u8 = 0x78; /// Integer, multiplication and division extension From 46752df2c90292499dfee261ddba86582e6ec165 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Thu, 26 Jan 2023 00:02:22 +0100 Subject: [PATCH 052/128] Add a first implementation to fix register zero issue --- src/simulator/machine.rs | 59 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 83be4a4..31e4993 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -1,8 +1,61 @@ +use std::ops::{Add, Sub}; + use super::{decode::{Instruction, decode}}; use super::global::*; /// doit disparaitre const MEM_SIZE : usize = 4096; +trait RegisterNum: Add + Sub + PartialEq + Copy {} + +impl RegisterNum for i64 {} + +impl RegisterNum for f32 {} + +struct Register { + register: [U; 32] +} + +impl Register { + + pub fn get_reg(&self, position: usize) -> U { + self.register[position] + } + +} + +impl Register { + + pub fn init() -> Register { + Register { + register: [0i64; 32] + } + } + + pub fn write_reg(&mut self, position: usize, value: i64) { + if position != 0 { + self.register[position] = value; + } else { + // Panic ou rien ? (dans le doute pour le moment panic) + unreachable!("You can't write to zero register") + } + } + +} + +impl Register { + + pub fn init() -> Register { + Register { + register: [0f32; 32] + } + } + + pub fn write_reg(&mut self, position: usize, value: f32) { + self.register[position] = value; + } + +} + pub struct Machine { pub pc : u64, pub int_reg : [i64 ; 32], @@ -26,13 +79,17 @@ impl Machine { value >>= 1; } + // let int_reg = Register::::init(); + // let fp_reg = Register::::init(); + Machine { pc : 0, instructions : [0 ; 100], int_reg : [0 ; 32], main_memory : [0 ; MEM_SIZE], shiftmask - } + } + } /// Read from main memory of the machine From 86ab1161e7879aa8d59b664dcf03bbf93ee50c1a Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Thu, 26 Jan 2023 00:08:49 +0100 Subject: [PATCH 053/128] function name more consistent --- src/simulator/machine.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 31e4993..e336842 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -31,7 +31,7 @@ impl Register { } } - pub fn write_reg(&mut self, position: usize, value: i64) { + pub fn set_reg(&mut self, position: usize, value: i64) { if position != 0 { self.register[position] = value; } else { @@ -50,7 +50,7 @@ impl Register { } } - pub fn write_reg(&mut self, position: usize, value: f32) { + pub fn set_reg(&mut self, position: usize, value: f32) { self.register[position] = value; } From 72b2a105f01af012c21e1a67a9f07c5b04d65bb7 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Fri, 27 Jan 2023 11:15:39 +0100 Subject: [PATCH 054/128] Add tests to machine --- src/simulator/machine.rs | 68 ++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 9 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e336842..26f4eae 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -139,10 +139,9 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions - pub fn run(machine : Machine){ - let mut m = machine; - loop{ - Machine::one_instruction(&mut m); + pub fn run(&mut self){ + loop { + self.one_instruction(); } } @@ -151,8 +150,8 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions and a pc to the actual instruction - pub fn one_instruction(machine :&mut Machine) { - + pub fn one_instruction(&mut self) { + let mut machine = self; let unsigned_reg1 : u64; let unsigned_reg2 : u64; let long_result : i128; @@ -466,11 +465,21 @@ impl Machine { #[cfg(test)] mod test { - use crate::simulator::machine::Machine; + use crate::simulator::{machine::Machine, decode}; + + + fn init() -> Machine { + let mut m = Machine::_init_machine(); + m.main_memory[0] = 255; + m.main_memory[1] = 43; + m.main_memory[2] = 7; + m.main_memory[3] = 157; + m + } #[test] fn test_read_memory() { - let mut m = Machine::_init_machine(); + let mut m = init(); m.main_memory[4] = 43; m.main_memory[5] = 150; assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); @@ -478,9 +487,50 @@ impl Machine { #[test] fn test_write_memory() { - let mut m = Machine::_init_machine(); + let mut m = init(); Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); assert_eq!(43, m.main_memory[6]); assert_eq!(150, m.main_memory[7]); } + + #[test] + fn test_op_add() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b0000000_00110_00000_000_00101_0110011; + // add t0, zero, t1 + m.one_instruction(); + assert_eq!(m.int_reg[5], 5); + } + + #[test] + fn test_op_sub() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b0100000_00110_00000_000_00101_0110011; + // sub t0, zero, t1 + m.one_instruction(); + assert_eq!(m.int_reg[5], -5); + } + + #[test] + fn test_op_addi() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b11111111111_00110_000_00101_0010011; + // add t0, t1, 2047 + m.one_instruction(); + assert_eq!(m.int_reg[5], 2052); + } + + /// Equivalent of subi + #[test] + fn test_op_addi_neg() { + let mut m = init(); + m.int_reg[6] = -5; // t1 + m.instructions[0] = 0b11111111111_00110_000_00101_0010011; + // addi t0, t1, 2047 + m.one_instruction(); + assert_eq!(m.int_reg[5], 2042); + } } From 5ad42a7073a5e42fc25169d9a2bed204583ba5b5 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 14:30:36 +0100 Subject: [PATCH 055/128] Revert "Add tests to machine" This reverts commit 72b2a105f01af012c21e1a67a9f07c5b04d65bb7. --- src/simulator/machine.rs | 68 ++++++---------------------------------- 1 file changed, 9 insertions(+), 59 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 26f4eae..e336842 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -139,9 +139,10 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions - pub fn run(&mut self){ - loop { - self.one_instruction(); + pub fn run(machine : Machine){ + let mut m = machine; + loop{ + Machine::one_instruction(&mut m); } } @@ -150,8 +151,8 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions and a pc to the actual instruction - pub fn one_instruction(&mut self) { - let mut machine = self; + pub fn one_instruction(machine :&mut Machine) { + let unsigned_reg1 : u64; let unsigned_reg2 : u64; let long_result : i128; @@ -465,21 +466,11 @@ impl Machine { #[cfg(test)] mod test { - use crate::simulator::{machine::Machine, decode}; - - - fn init() -> Machine { - let mut m = Machine::_init_machine(); - m.main_memory[0] = 255; - m.main_memory[1] = 43; - m.main_memory[2] = 7; - m.main_memory[3] = 157; - m - } + use crate::simulator::machine::Machine; #[test] fn test_read_memory() { - let mut m = init(); + let mut m = Machine::_init_machine(); m.main_memory[4] = 43; m.main_memory[5] = 150; assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); @@ -487,50 +478,9 @@ impl Machine { #[test] fn test_write_memory() { - let mut m = init(); + let mut m = Machine::_init_machine(); Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); assert_eq!(43, m.main_memory[6]); assert_eq!(150, m.main_memory[7]); } - - #[test] - fn test_op_add() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b0000000_00110_00000_000_00101_0110011; - // add t0, zero, t1 - m.one_instruction(); - assert_eq!(m.int_reg[5], 5); - } - - #[test] - fn test_op_sub() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b0100000_00110_00000_000_00101_0110011; - // sub t0, zero, t1 - m.one_instruction(); - assert_eq!(m.int_reg[5], -5); - } - - #[test] - fn test_op_addi() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b11111111111_00110_000_00101_0010011; - // add t0, t1, 2047 - m.one_instruction(); - assert_eq!(m.int_reg[5], 2052); - } - - /// Equivalent of subi - #[test] - fn test_op_addi_neg() { - let mut m = init(); - m.int_reg[6] = -5; // t1 - m.instructions[0] = 0b11111111111_00110_000_00101_0010011; - // addi t0, t1, 2047 - m.one_instruction(); - assert_eq!(m.int_reg[5], 2042); - } } From 069a8e57414ac63fe2b9d75103f70db3a7124701 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 16:39:40 +0100 Subject: [PATCH 056/128] Using a struct for registers instead of an array --- src/simulator/machine.rs | 72 +++++++++++++++++----------------------- src/simulator/mod.rs | 2 +- 2 files changed, 31 insertions(+), 43 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e336842..45bafe7 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -58,7 +58,7 @@ impl Register { pub struct Machine { pub pc : u64, - pub int_reg : [i64 ; 32], + pub int_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -85,7 +85,7 @@ impl Machine { Machine { pc : 0, instructions : [0 ; 100], - int_reg : [0 ; 32], + int_reg : Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -175,19 +175,19 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); }, RISCV_AUIPC => { - machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); }, RISCV_JAL => { - machine.int_reg[inst.rd as usize] = machine.pc as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); machine.pc += inst.imm21_1_signed as u64 - 4; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; - machine.int_reg[inst.rd as usize] = tmp as i64; + machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg.set_reg(inst.rd as usize, tmp as i64); }, //****************************************************************************************** @@ -195,32 +195,32 @@ impl Machine { RISCV_BR => { match inst.funct3 { RISCV_BR_BEQ => { - if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BNE => { - if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGE => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLTU => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGEU => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, @@ -234,49 +234,37 @@ impl Machine { // Treatment for: LOAD INSTRUCTIONS RISCV_LD => { match inst.funct3 { - RISCV_LD_LB => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LB | RISCV_LD_LBU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LH => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LH | RISCV_LD_LHU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LW => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LW | RISCV_LD_LWU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, RISCV_LD_LD => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - - // same thing three opration ? - RISCV_LD_LBU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LHU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LWU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); } } }, - // store instructions RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { - Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici + Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STH => { - Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STW => { - Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STD => { - Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, _ => { panic!("In ST switch case, this should never happen... Instr was {}", inst.value); @@ -288,22 +276,22 @@ impl Machine { RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64); }, RISCV_OPI_SLTI => { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; + machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } ); }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64); }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64); }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64); }, RISCV_OPI_SLLI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt); }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 6aef6be..266e97a 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -167,7 +167,7 @@ pub mod global { /// /// Store doubleword (SD) (64 bits) /// - /// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` + /// `SD rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STD: u8 = 0x3; /// Type: I From ff0d10edb59aac31f48f3a0cdcc3fade2848f419 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Feb 2023 16:41:49 +0100 Subject: [PATCH 057/128] add floating point instructions --- src/simulator/machine.rs | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 83be4a4..4965234 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -398,6 +398,114 @@ impl Machine { } } } + }, + //****************************************************************************************** + // Treatment for: Simple floating point extension + RISCV_FP => { + match inst.funct7 { + RISCV_FP_ADD => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_SUB => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_MUL => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_DIV => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_SQRT => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt(); + }, + RISCV_FP_FSGN => { + let local_float = machine.fp_reg[inst.rs1 as usize]; + match inst.funct3 { + RISCV_FP_FSGN_J => { + if machine.fp_reg[inst.rs2 as usize] < 0 { + machine.fp_reg[inst.rd as usize] = -local_float; + } else { + machine.fp_reg[inst.rd as usize] = local_float; + } + } + RISCV_FP_FSGN_JN => { + if machine.fp_reg[inst.rs2 as usize] < 0 { + machine.fp_reg[inst.rd as usize] = local_float; + } else { + machine.fp_reg[inst.rd as usize] = -local_float; + } + } + RISCV_FP_FSGN_JX => { + if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) { + machine.fp_reg[inst.rd as usize] = -local_float; + } else { + machine.fp_reg[inst.rd as usize] = local_float; + } + } + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + RISCV_FP_MINMAX => { + let r1 = machine.fp_reg[inst.rs1 as usize]; + let r2 = machine.fp_reg[inst.rs2 as usize]; + match inst.funct3 { + RISCV_FP_MINMAX_MIN => { + machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2} + }, + RISCV_FP_MINMAX_MAX => { + machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2} + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + RISCV_FP_FCVTW => { + if inst.rs2 == RISCV_FP_FCVTW_W { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + } else { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64; + } + }, + RISCV_FP_FCVTS => { + if inst.rs2 == RISCV_FP_FCVTS_W { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + } else { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32; + } + }, + RISCV_FP_FMVW => { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + }, + RISCV_FP_FMVXFCLASS => { + if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + } else { + panic!("Fclass instruction is not handled in riscv simulator"); + } + }, + RISCV_FP_FCMP => { + match inst.funct3 { + RISCV_FP_FCMP_FEQ => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + RISCV_FP_FCMP_FLT => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + RISCV_FP_FCMP_FLE => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } } _ => { panic!("{} opcode non géré", inst.opcode)}, } From 4d2e92021c53c24847e9349e0b65d2cb073306dd Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 1 Feb 2023 16:57:40 +0100 Subject: [PATCH 058/128] Added a test on a small program and removed unnecessary spaces --- src/simulator/print.rs | 107 +++++++++++++++++++++++++++-------------- 1 file changed, 70 insertions(+), 37 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 8544334..ea8cd2a 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -13,7 +13,7 @@ const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; // Register name mapping -const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? +const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", // fp ou s0 ? "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"]; @@ -62,9 +62,9 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } } else if ins.funct3 == RISCV_OPI_SLLI { - format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) + format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) + format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_LUI => { @@ -81,24 +81,16 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_JALR => { - if ins.rd == 0 { - if ins.rs1 == 1 { - "ret".to_string() - } else { - format!("jr\t{:X}", ins.imm31_12) - } - } else { - format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1]) - } + format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_BR => { format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed) }, RISCV_LD => { - format!("{}\t{}, {}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) + format!("{}\t{},{}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_ST => { - format!("{}\t{}, {}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1]) + format!("{}\t{},{}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1]) }, RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { @@ -118,18 +110,18 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { - format!("addw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("subw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("subw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPW_SRW { if ins.funct7 == RISCV_OPW_SRW_SRLW { - format!("srlw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("srlw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("sraw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("sraw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else { - format!("{}\t{}, {}, {}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}\t{},{},{}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } }, RISCV_SYSTEM => { @@ -173,13 +165,13 @@ mod test { let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011); let andi = decode::decode(0b000000000000_10001_111_11100_0010011); - assert_eq!("andi\tt3, a7, 0", print::print(andi, 0)); - assert_eq!("addi\tt3, a7, 0", print::print(addi, 0)); - assert_eq!("slli\tt3, a7, 0", print::print(slli, 0)); - assert_eq!("slti\tt3, a7, 0", print::print(slti, 0)); - assert_eq!("sltiu\tt3, a7, 0", print::print(sltiu, 0)); - assert_eq!("xori\tt3, a7, 0", print::print(xori, 0)); - assert_eq!("ori\tt3, a7, 0", print::print(ori, 0)); + assert_eq!("andi\tt3,a7,0", print::print(andi, 0)); + assert_eq!("addi\tt3,a7,0", print::print(addi, 0)); + assert_eq!("slli\tt3,a7,0", print::print(slli, 0)); + assert_eq!("slti\tt3,a7,0", print::print(slti, 0)); + assert_eq!("sltiu\tt3,a7,0", print::print(sltiu, 0)); + assert_eq!("xori\tt3,a7,0", print::print(xori, 0)); + assert_eq!("ori\tt3,a7,0", print::print(ori, 0)); } #[test] @@ -201,13 +193,13 @@ mod test { let ld = decode::decode(0b010111110000_10001_011_11100_0000011); let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); - assert_eq!("lb\tt3, 1520(a7)", print::print(lb, 0)); - assert_eq!("lh\tt3, 1520(a7)", print::print(lh, 0)); - assert_eq!("lw\tt3, 1520(a7)", print::print(lw, 0)); - assert_eq!("lbu\tt3, 1520(a7)", print::print(lbu, 0)); - assert_eq!("lhu\tt3, 1520(a7)", print::print(lhu, 0)); - assert_eq!("ld\tt3, 1520(a7)", print::print(ld, 0)); - assert_eq!("lwu\tt3, 1520(a7)", print::print(lwu, 0)); + assert_eq!("lb\tt3,1520(a7)", print::print(lb, 0)); + assert_eq!("lh\tt3,1520(a7)", print::print(lh, 0)); + assert_eq!("lw\tt3,1520(a7)", print::print(lw, 0)); + assert_eq!("lbu\tt3,1520(a7)", print::print(lbu, 0)); + assert_eq!("lhu\tt3,1520(a7)", print::print(lhu, 0)); + assert_eq!("ld\tt3,1520(a7)", print::print(ld, 0)); + assert_eq!("lwu\tt3,1520(a7)", print::print(lwu, 0)); } #[test] @@ -217,10 +209,10 @@ mod test { let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); - assert_eq!("addw\tt3, a7, a6", print::print(addw, 0)); - assert_eq!("sllw\tt3, a7, a6", print::print(sllw, 0)); - assert_eq!("srlw\tt3, a7, a6", print::print(srlw, 0)); - assert_eq!("sraw\tt3, a7, a6", print::print(sraw, 0)); + assert_eq!("addw\tt3,a7,a6", print::print(addw, 0)); + assert_eq!("sllw\tt3,a7,a6", print::print(sllw, 0)); + assert_eq!("srlw\tt3,a7,a6", print::print(srlw, 0)); + assert_eq!("sraw\tt3,a7,a6", print::print(sraw, 0)); } #[test] @@ -250,4 +242,45 @@ mod test { assert_eq!("beq\ta7, a6, 0", print::print(beq, 0)); } + #[test] + fn test_small_program() { + /* Code for : + int a = 0; + int b = 5; + a = b; + a = a * b; + a = a + b; + b = a - b; + */ + assert_eq!("addi sp,sp,-32", print::print(decode::decode(0xfe010113), 0)); + assert_eq!("sd s0,24(sp)", print::print(decode::decode(0x00813c23), 0)); + assert_eq!("addi s0,sp,32", print::print(decode::decode(0x02010413), 0)); + assert_eq!("sw zero,-20(s0)", print::print(decode::decode(0xfe042623), 0)); + assert_eq!("addi a5,zero,5", print::print(decode::decode(0x00500793), 0)); + assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); + assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + //assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); + assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + assert_eq!("addw a5,a4,a5", print::print(decode::decode(0x00f707bb), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); + assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + assert_eq!("subw a5,a4,a5", print::print(decode::decode(0x40f707bb), 0)); + assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0)); + assert_eq!("addi a5,zero,0", print::print(decode::decode(0x00000793), 0)); + assert_eq!("addi a0,a5,0", print::print(decode::decode(0x00078513), 0)); + assert_eq!("ld s0,24(sp)", print::print(decode::decode(0x01813403), 0)); + assert_eq!("addi sp,sp,32", print::print(decode::decode(0x02010113), 0)); + assert_eq!("jalr zero,0(ra)", print::print(decode::decode(0x00008067), 0)); + + } + } \ No newline at end of file From 1efcd73ae71da17fe1016ba03b3cdfe3e9d6d376 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Feb 2023 17:02:19 +0100 Subject: [PATCH 059/128] OPW & OP for funct7 == -1 --- src/simulator/machine.rs | 60 ++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 45bafe7..ae9511e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -342,42 +342,42 @@ impl Machine { match inst.funct3 { RISCV_OP_ADD => { if inst.funct7 == RISCV_OP_ADD_ADD { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize)); } else { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize)); } }, RISCV_OP_SLL => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f)); }, RISCV_OP_SLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { - machine.int_reg[inst.rd as usize] = 1; + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { + machine.int_reg.set_reg(inst.rd as usize, 1); } else { - machine.int_reg[inst.rd as usize] = 0; + machine.int_reg.set_reg(inst.rd as usize, 0); } }, RISCV_OP_SLTU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; if unsigned_reg1 < unsigned_reg2 { - machine.int_reg[inst.rd as usize] = 1; + machine.int_reg.set_reg(inst.rd as usize, 1); } else { - machine.int_reg[inst.rd as usize] = 0; + machine.int_reg.set_reg(inst.rd as usize, 0); } }, RISCV_OP_XOR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_SR => { // RISCV_OP_SR_SRL inaccessible - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_OR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_AND => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize)); }, _ => { panic!("RISCV_OP undefined case\n"); @@ -389,53 +389,53 @@ impl Machine { // Treatment for: OPW INSTRUCTIONS RISCV_OPW => { if inst.funct7 == 1 { - let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff; - let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; + let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; // Match case for multiplication operations (in standard extension RV32M) match inst.funct3 { RISCV_OPW_M_MULW => { - machine.int_reg[inst.rd as usize] = local_data_a * local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b); }, RISCV_OPW_M_DIVW => { - machine.int_reg[inst.rd as usize] = local_data_a / local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b); }, RISCV_OPW_M_DIVUW => { - machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned; + machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned); }, RISCV_OPW_M_REMW => { - machine.int_reg[inst.rd as usize] = local_data_a % local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b); }, RISCV_OPW_M_REMUW => { - machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned; + machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned); }, _ => { panic!("this instruction ({}) doesn't exists", inst.value); } } } else { - let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; // Match case for base OP operation match inst.funct3 { RISCV_OPW_ADDSUBW => { if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { - machine.int_reg[inst.rd as usize] = local_dataa + local_datab; + machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab); } else { // SUBW - machine.int_reg[inst.rd as usize] = local_dataa - local_datab; + machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab); } }, RISCV_OPW_SLLW => { - machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f); + machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f)); }, RISCV_OPW_SRW => { if inst.funct7 == RISCV_OPW_SRW_SRLW { - machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64; + machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64); } else { // SRAW - machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f); + machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f)); } }, _ => { From 67ebff7ad06ae88d49246f704dd25330e615fa6b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:04:10 +0100 Subject: [PATCH 060/128] Update registers access on RISCV_OP --- src/simulator/machine.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 45bafe7..d27dc60 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -295,9 +295,9 @@ impl Machine { }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; + machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); } else { // SRAI - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt); } } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } @@ -308,17 +308,17 @@ impl Machine { if inst.funct7 == 1 { match inst.funct3 { RISCV_OP_M_MUL => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULH => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULHSU => { - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; - long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -326,13 +326,13 @@ impl Machine { * WHAT DA HECK */ RISCV_OP_M_MULHU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_DIV => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize)); } _ => { panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); From 0e89061a031ad6858b1e433164887e19dc396bd9 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:10:11 +0100 Subject: [PATCH 061/128] Fix errors preventing compiling --- src/simulator/machine.rs | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 2c6f035..b22d576 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -5,13 +5,13 @@ use super::global::*; /// doit disparaitre const MEM_SIZE : usize = 4096; -trait RegisterNum: Add + Sub + PartialEq + Copy {} +pub trait RegisterNum: Add + Sub + PartialEq + Copy {} impl RegisterNum for i64 {} impl RegisterNum for f32 {} -struct Register { +pub struct Register { register: [U; 32] } @@ -235,16 +235,20 @@ impl Machine { RISCV_LD => { match inst.funct3 { RISCV_LD_LB | RISCV_LD_LBU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LH | RISCV_LD_LHU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LW | RISCV_LD_LWU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LD => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); From 658502d3532830bdaeac536b2e88769514761ace Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:26:34 +0100 Subject: [PATCH 062/128] Convert some fp reg from array to struct call --- src/simulator/machine.rs | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 913abda..4d4ee63 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -59,6 +59,7 @@ impl Register { pub struct Machine { pub pc : u64, pub int_reg : Register, + pub fp_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -86,6 +87,7 @@ impl Machine { pc : 0, instructions : [0 ; 100], int_reg : Register::::init(), + fp_reg: Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -453,19 +455,19 @@ impl Machine { RISCV_FP => { match inst.funct7 { RISCV_FP_ADD => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_SUB => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_MUL => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_DIV => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_SQRT => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt(); + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt()); }, RISCV_FP_FSGN => { let local_float = machine.fp_reg[inst.rs1 as usize]; From 1c6606eb35c7fa7ecb5befc9aae8bf7718612187 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Feb 2023 17:29:31 +0100 Subject: [PATCH 063/128] impl register for floating point (from bottom) --- src/simulator/machine.rs | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 913abda..3a5fbfa 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -59,6 +59,7 @@ impl Register { pub struct Machine { pub pc : u64, pub int_reg : Register, + pub fp_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -86,6 +87,7 @@ impl Machine { pc : 0, instructions : [0 ; 100], int_reg : Register::::init(), + fp_reg : Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -485,10 +487,10 @@ impl Machine { } } RISCV_FP_FSGN_JX => { - if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) { - machine.fp_reg[inst.rd as usize] = -local_float; + if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) { + machine.fp_reg.set_reg(inst.rd as usize, -local_float); } else { - machine.fp_reg[inst.rd as usize] = local_float; + machine.fp_reg.set_reg(inst.rd as usize, local_float); } } _ => { @@ -497,14 +499,14 @@ impl Machine { } }, RISCV_FP_MINMAX => { - let r1 = machine.fp_reg[inst.rs1 as usize]; - let r2 = machine.fp_reg[inst.rs2 as usize]; + let r1 = machine.fp_reg.get_reg(inst.rs1 as usize); + let r2 = machine.fp_reg.get_reg(inst.rs2 as usize); match inst.funct3 { RISCV_FP_MINMAX_MIN => { - machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2} + machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2}); }, RISCV_FP_MINMAX_MAX => { - machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2} + machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2}); }, _ => { panic!("this instruction ({}) doesn't exists", inst.value); @@ -513,24 +515,24 @@ impl Machine { }, RISCV_FP_FCVTW => { if inst.rs2 == RISCV_FP_FCVTW_W { - machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64); } else { - machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64; + machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64); } }, RISCV_FP_FCVTS => { if inst.rs2 == RISCV_FP_FCVTS_W { - machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32); } else { - machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32; + machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32); } }, RISCV_FP_FMVW => { - machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32); }, RISCV_FP_FMVXFCLASS => { if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { - machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64); } else { panic!("Fclass instruction is not handled in riscv simulator"); } @@ -538,13 +540,13 @@ impl Machine { RISCV_FP_FCMP => { match inst.funct3 { RISCV_FP_FCMP_FEQ => { - machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0}; + machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); }, RISCV_FP_FCMP_FLT => { - machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0}; + machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); }, RISCV_FP_FCMP_FLE => { - machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0}; + machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); }, _ => { panic!("this instruction ({}) doesn't exists", inst.value); From 32a08caec241e1ba9f6e0f3cb4c342a6ae35d878 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 1 Feb 2023 17:30:18 +0100 Subject: [PATCH 064/128] Fixed JAL --- src/simulator/print.rs | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index ea8cd2a..68a8b89 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -74,11 +74,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { - if ins.rd == 0 { - format!("j\t{}", ins.imm31_12) - } else { - format!("jal\t{}, {:X}", REG_X[rd], (pc - 4 + ins.imm21_1_signed)) - } + format!("jal\t{},{:X}", REG_X[rd], (pc + ins.imm21_1_signed)) }, RISCV_JALR => { format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) @@ -263,7 +259,7 @@ mod test { assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); - //assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); + //Waiting for mulw implementation assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); @@ -283,4 +279,11 @@ mod test { } + + #[test] + fn test_fibo() { + assert_eq!("jal zero,10504", print::print(decode::decode(0x0500006f), 0x104b4)); + //assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); + } + } \ No newline at end of file From bce7047c5c703ddbf56cdf2f9af729e0eb68e651 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:32:17 +0100 Subject: [PATCH 065/128] Convert some fp reg from array to struct call --- src/simulator/machine.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 4d4ee63..1981c8e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -470,20 +470,20 @@ impl Machine { machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt()); }, RISCV_FP_FSGN => { - let local_float = machine.fp_reg[inst.rs1 as usize]; + let local_float = machine.fp_reg.get_reg(inst.rs1 as usize); match inst.funct3 { RISCV_FP_FSGN_J => { - if machine.fp_reg[inst.rs2 as usize] < 0 { - machine.fp_reg[inst.rd as usize] = -local_float; + if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 { + machine.fp_reg.set_reg(inst.rd as usize, -local_float); } else { - machine.fp_reg[inst.rd as usize] = local_float; + machine.fp_reg.set_reg(inst.rd as usize, local_float); } } RISCV_FP_FSGN_JN => { - if machine.fp_reg[inst.rs2 as usize] < 0 { - machine.fp_reg[inst.rd as usize] = local_float; + if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 { + machine.fp_reg.set_reg(inst.rd as usize, local_float); } else { - machine.fp_reg[inst.rd as usize] = -local_float; + machine.fp_reg.set_reg(inst.rd as usize, -local_float); } } RISCV_FP_FSGN_JX => { From 37625474020b6c343e5ba858b629ed7e73f4c947 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Sat, 4 Feb 2023 18:16:52 +0100 Subject: [PATCH 066/128] Added OPIW OPs and made some fix (see description) Fix some warning which appear on clippy Fix print with 2 OPIW operations Fix doc in mod.rs --- src/main.rs | 2 +- src/simulator/machine.rs | 37 ++++++++++++++++++++++++++++++++----- src/simulator/mod.rs | 6 +++--- src/simulator/print.rs | 4 ++-- 4 files changed, 38 insertions(+), 11 deletions(-) diff --git a/src/main.rs b/src/main.rs index 953914e..4acaaf7 100644 --- a/src/main.rs +++ b/src/main.rs @@ -9,6 +9,6 @@ fn main() { let a : u8 = 128; let b : i8 = a as i8; let c : u8 = b as u8; - println!("aaa {}", c); + println!("aaa {c}"); println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4)); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index c8a6fd6..44888f4 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -105,7 +105,7 @@ impl Machine { /// - **address** in the memory to read pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { if ![1, 2, 4, 8].contains(&size) { - panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); + panic!("ERROR read_memory : wrong size parameter {size}, must be (1, 2, 4 or 8)"); } let mut ret: u64 = 0; @@ -128,11 +128,11 @@ impl Machine { /// - **value** data to be written pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) { if ![1, 2, 4, 8].contains(&size) { - panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size) + panic!("ERROR write_memory: WRONG `size` PARAMETER ({size}), must be 1, 2, 4 or 8") } for i in 0..size as usize { let inv_i = size as usize - i - 1; - machine.main_memory[address + i as usize] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8; + machine.main_memory[address + i] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8; } } @@ -392,9 +392,36 @@ impl Machine { } }, //****************************************************************************************** + // Treatment for OPIW INSTRUCTIONS + RISCV_OPIW => { + let local_data = machine.int_reg.get_reg(inst.rs1 as usize); + match inst.funct3 { + RISCV_OPIW_ADDIW => { + let result = local_data + inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, result); + }, + RISCV_OPIW_SLLIW => { + let result = local_data << inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, result); + }, + RISCV_OPIW_SRW => { + let result; + if inst.funct7 == RISCV_OPIW_SRW_SRLIW { + result = (local_data >> inst.shamt) & machine.shiftmask[32 + inst.shamt as usize] as i64; + } else { // SRAIW + result = local_data >> inst.shamt; + } + machine.int_reg.set_reg(inst.rd as usize, result); + }, + _ => { + panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value); + } + } + }, + //****************************************************************************************** // Treatment for: OPW INSTRUCTIONS RISCV_OPW => { - if inst.funct7 == 1 { + if inst.funct7 == 1 { // rv64m let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; @@ -421,7 +448,7 @@ impl Machine { panic!("this instruction ({}) doesn't exists", inst.value); } } - } else { + } else { // others rv64 OPW operations let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 266e97a..16e19a5 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -303,7 +303,7 @@ pub mod global { /// /// Shift right logical immediate word (RV64I only) /// - /// `SLLIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + /// `SLLIW rd, rs1, imm12` => `rd <- rs1 >> shamt` pub const RISCV_OPIW_SLLIW: u8 = 0x1; /// Shift right immediate instructions (logical or arithmetic depend of func7) @@ -312,7 +312,7 @@ pub mod global { /// /// Shift right logical immediate word (RV64I only) /// - /// `SRLIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + /// `SRLIW rd, rs1, imm12` => `rd <- rs1 >> shamt` /// /// Complete left bits by a zero, should be used with an unsigned value in most case pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; @@ -320,7 +320,7 @@ pub mod global { /// /// Shift right arithmetic immediate word (RV64I only) /// - /// `SRAIW rd, rs1, imm12` => `rd <- rs1 >> imm12` + /// `SRAIW rd, rs1, imm12` => `rd <- rs1 >> shamt` /// /// Keep sign bit pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 68a8b89..4bad5ad 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -91,9 +91,9 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srlwi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("srliw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("srawi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("sraiw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) From 2d9c3f4ea3dc112eeeb4bbfdee13b3957c9296dd Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Tue, 7 Feb 2023 15:19:38 +0100 Subject: [PATCH 067/128] squelette mem_cmp --- src/simulator/mem_cmp.rs | 60 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 src/simulator/mem_cmp.rs diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs new file mode 100644 index 0000000..7da05f7 --- /dev/null +++ b/src/simulator/mem_cmp.rs @@ -0,0 +1,60 @@ +/* TRUCS MANQUANT +* Verifier qu'il y a un nombre pair de caractere hexa dans la ligne correspondante d'une section du fichier source +* Sinon on ne peut pas automatiquement remplir chaque octect car 2 hexa = 1 octet +*/ + + + + +/* FORMAT FICHIER.TXT Représentant la mémoire apres éxecution d'un prog +* PC +* SP +* Section_1 +* Section_2 +* ... +* ... +* Section_n +*/ + +/* Chaque section se divise en 3 parties, sur 2 lignes de texte +* addr ESPACE len +* content +*/ + +//content est une suite hexadécimale + +//Section dans le fichier, champ String car informations proviennent d'un fichier txt +struct SectionFormat{ + addr: String, + len: String, + content: String, +} + +//Section dans le programme +struct Section{ + addr: usize, // adresse dans la mémoire + len: usize, // nombre d'octets de la donnée à addr + content: Vec, // la donnée en question +} + + + + +/* +* Voir si instanciation d'une structure deplace les valeurs "locales" à la méthode from, je sais plus .... + */ +impl Section{ + fn from(section: &SectionFormat) -> Section { + let mut content: Vec = Vec::new(); + let addr: usize = section.addr.parse().unwrap(); + let len: usize = section.len.parse().unwrap(); + + /* + * Remplissage de content + */ + + + Section{addr:addr, len:len, content:content} + } +} + From f9046f411aceae85c6d6a2693bc8b2bccc0d411c Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 21:58:02 +0100 Subject: [PATCH 068/128] Fixed print for BR --- src/simulator/print.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 4bad5ad..a76fbd6 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -80,7 +80,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_BR => { - format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed) + format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32)) }, RISCV_LD => { format!("{}\t{},{}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) @@ -230,12 +230,12 @@ mod test { let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); - assert_eq!("blt\ta7, a6, 0", print::print(blt, 0)); - assert_eq!("bge\ta7, a6, 0", print::print(bge, 0)); - assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0)); - assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0)); - assert_eq!("bne\ta7, a6, 0", print::print(bne, 0)); - assert_eq!("beq\ta7, a6, 0", print::print(beq, 0)); + assert_eq!("blt\ta7,a6,0", print::print(blt, 0)); + assert_eq!("bge\ta7,a6,0", print::print(bge, 0)); + assert_eq!("bltu\ta7,a6,0", print::print(bltu, 0)); + assert_eq!("bgeu\ta7,a6,0", print::print(bgeu, 0)); + assert_eq!("bne\ta7,a6,0", print::print(bne, 0)); + assert_eq!("beq\ta7,a6,0", print::print(beq, 0)); } #[test] @@ -283,7 +283,7 @@ mod test { #[test] fn test_fibo() { assert_eq!("jal zero,10504", print::print(decode::decode(0x0500006f), 0x104b4)); - //assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); + assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); } } \ No newline at end of file From 89aaa4e821da2a88f86eb4e5706d913c401e94b3 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 22:00:53 +0100 Subject: [PATCH 069/128] Changed hexa format to lowercase --- src/simulator/print.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index a76fbd6..e6d5a54 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -68,13 +68,13 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12) + format!("lui\t{}, 0x{:x}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12) + format!("auipc\t{}, {:x}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { - format!("jal\t{},{:X}", REG_X[rd], (pc + ins.imm21_1_signed)) + format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed)) }, RISCV_JALR => { format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) @@ -174,8 +174,8 @@ mod test { fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0)); - assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0)); + assert_eq!("lui\tt3, 0x710f8000", print::print(lui, 0)); + assert_eq!("lui\tt3, 0xf10f8000", print::print(lui_negatif, 0)); } #[test] From 4438218d339a2aba45d2573914e4ab2ede3b4295 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 22:05:35 +0100 Subject: [PATCH 070/128] Removed wrong spaces --- src/simulator/print.rs | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index e6d5a54..6e18925 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -51,15 +51,15 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } else { name = NAMES_OP[ins.funct3 as usize]; } - format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}\t{},{},{}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("srli\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) + format!("srli\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) + format!("srai\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt) } } else if ins.funct3 == RISCV_OPI_SLLI { format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) @@ -68,10 +68,10 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui\t{}, 0x{:x}", REG_X[rd], ins.imm31_12) + format!("lui\t{},{:x}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:x}", REG_X[rd], ins.imm31_12) + format!("auipc\t{},{:x}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed)) @@ -91,19 +91,19 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srliw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("srliw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("sraiw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) + format!("{}\t{},{},{}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}w\t{},{},{}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) @@ -144,11 +144,11 @@ mod test { let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); - assert_eq!("sub\tt3, a7, a6", print::print(sub, 0)); - assert_eq!("xor\tt3, a7, a6", print::print(xor, 0)); - assert_eq!("srl\tt3, a7, a6", print::print(slr, 0)); - assert_eq!("sra\tt3, a7, a6", print::print(sra, 0)); - assert_eq!("add\tt3, a7, a6", print::print(add, 0)); + assert_eq!("sub\tt3,a7,a6", print::print(sub, 0)); + assert_eq!("xor\tt3,a7,a6", print::print(xor, 0)); + assert_eq!("srl\tt3,a7,a6", print::print(slr, 0)); + assert_eq!("sra\tt3,a7,a6", print::print(sra, 0)); + assert_eq!("add\tt3,a7,a6", print::print(add, 0)); } @@ -174,8 +174,8 @@ mod test { fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui\tt3, 0x710f8000", print::print(lui, 0)); - assert_eq!("lui\tt3, 0xf10f8000", print::print(lui_negatif, 0)); + assert_eq!("lui\tt3,710f8000", print::print(lui, 0)); + assert_eq!("lui\tt3,f10f8000", print::print(lui_negatif, 0)); } #[test] @@ -216,9 +216,9 @@ mod test { let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); - assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0)); - assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0)); - assert_eq!("srai\tt3, a7, 17", print::print(srai, 0)); + assert_eq!("addiw\tt3,a7,0", print::print(addiw, 0)); + assert_eq!("slli\tt3,a7,a6", print::print(slliw, 0)); + assert_eq!("srai\tt3,a7,17", print::print(srai, 0)); } From 9978818444ffe36d431f1a17bdc4990c0e8dc21d Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Tue, 7 Feb 2023 22:40:53 +0100 Subject: [PATCH 071/128] test creation section + conversion hexa --- src/simulator/mem_cmp.rs | 109 +++++++++++++++++++++++++++++++++++++-- src/simulator/mod.rs | 1 + 2 files changed, 107 insertions(+), 3 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 7da05f7..41bcf3a 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -37,8 +37,33 @@ struct Section{ content: Vec, // la donnée en question } +/* +* c doit etre un caractère hexadécimale + */ +fn one_hex_to_dec(c: char) -> u8 { + match c { + 'A' | 'a' => 10, + 'B' | 'b' => 11, + 'C' | 'c' => 12, + 'D' | 'd' => 13, + 'E' | 'e' => 14, + 'F' | 'f' => 15, + _ => { + let ret : u8 = c.to_digit(10).unwrap() as u8; + return ret; + }, + } + } + + +fn two_hex_to_u8(c1: char, c2: char) -> u8 { + let a = one_hex_to_dec(c1); + let b = one_hex_to_dec(c2); + + 16*a + b +} /* * Voir si instanciation d'une structure deplace les valeurs "locales" à la méthode from, je sais plus .... @@ -49,12 +74,90 @@ impl Section{ let addr: usize = section.addr.parse().unwrap(); let len: usize = section.len.parse().unwrap(); - /* - * Remplissage de content - */ + let mut tmp_a: char = ' '; + let mut tmp_b: char = ' '; + + for (i, c) in section.content.chars().enumerate(){ + + if i%2 == 0 { + tmp_a = c; + } + else { + tmp_b = c; + content.push(two_hex_to_u8(tmp_a,tmp_b)); + } + } Section{addr:addr, len:len, content:content} } } +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_create_section_content(){ + let section_format = SectionFormat{ + addr: "0".to_string(), + len: "0".to_string(), + content: "00FF0AA0A5".to_string(), + }; + + let section = Section::from(§ion_format); + let mut expected_vec: Vec = Vec::new(); + expected_vec.push(0u8); + expected_vec.push(255u8); + expected_vec.push(10u8); + expected_vec.push(160u8); + expected_vec.push(165u8); + + //println!("Vec from created section {:?}", §ion.content); + //println!("Expected vec {:?}", &expected_vec); + + assert_eq!(section.content, expected_vec); + } + + #[test] + fn test_mod(){ + let cond = (0%2) == 0; + assert_eq!(true, cond); + } + + #[test] + fn test_mod_2(){ + let cond = (1%2) == 1; + assert_eq!(true, cond); + } + + #[test] + fn test_hex_1(){ + let b = two_hex_to_u8('0', '0'); + assert_eq!(0u8, b); + } + + #[test] + fn test_hex_2(){ + let b = two_hex_to_u8('F', 'F'); + assert_eq!(255u8, b); + } + + #[test] + fn test_hex_3(){ + let b = two_hex_to_u8('0', 'A'); + assert_eq!(10u8, b); + } + + #[test] + fn test_hex_4(){ + let b = two_hex_to_u8('A', '0'); + assert_eq!(160u8, b); + } + + #[test] + fn test_hex_5(){ + let b = two_hex_to_u8('A', '5'); + assert_eq!(165u8, b); + } +} \ No newline at end of file diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 16e19a5..76c2931 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -1,6 +1,7 @@ pub mod machine; pub mod decode; pub mod print; +mod mem_cmp; pub mod global { From 70210699a467c918d0b8b299f6c499d54ca8b1a1 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Tue, 7 Feb 2023 22:50:55 +0100 Subject: [PATCH 072/128] squelette Mem_Checker --- src/simulator/mem_cmp.rs | 78 +++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 28 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 41bcf3a..859bfad 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -37,34 +37,6 @@ struct Section{ content: Vec, // la donnée en question } -/* -* c doit etre un caractère hexadécimale - */ -fn one_hex_to_dec(c: char) -> u8 { - - match c { - 'A' | 'a' => 10, - 'B' | 'b' => 11, - 'C' | 'c' => 12, - 'D' | 'd' => 13, - 'E' | 'e' => 14, - 'F' | 'f' => 15, - _ => { - let ret : u8 = c.to_digit(10).unwrap() as u8; - return ret; - }, - } - } - - - -fn two_hex_to_u8(c1: char, c2: char) -> u8 { - let a = one_hex_to_dec(c1); - let b = one_hex_to_dec(c2); - - 16*a + b -} - /* * Voir si instanciation d'une structure deplace les valeurs "locales" à la méthode from, je sais plus .... */ @@ -93,6 +65,51 @@ impl Section{ } } +/* +* Representation de l'etat de la mémoire (apres execution.... a confirmer), sous forme de sections +*/ +struct Mem_Checker{ + pc: usize, + sp: usize, + sections: Vec
, +} + + +impl Mem_Checker{ + /*fn from(path: &String) -> Mem_Checker{ + + }*/ +} + + +/* +* c doit etre un caractère hexadécimale + */ +fn one_hex_to_dec(c: char) -> u8 { + + match c { + 'A' | 'a' => 10, + 'B' | 'b' => 11, + 'C' | 'c' => 12, + 'D' | 'd' => 13, + 'E' | 'e' => 14, + 'F' | 'f' => 15, + _ => { + let ret : u8 = c.to_digit(10).unwrap() as u8; + return ret; + }, + } + } + + + +fn two_hex_to_u8(c1: char, c2: char) -> u8 { + let a = one_hex_to_dec(c1); + let b = one_hex_to_dec(c2); + + 16*a + b +} + #[cfg(test)] mod tests { use super::*; @@ -119,6 +136,11 @@ mod tests { assert_eq!(section.content, expected_vec); } + + + + + #[test] fn test_mod(){ let cond = (0%2) == 0; From 3e8d68be544ee9162040d340d26b817e869227ab Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 23:14:29 +0100 Subject: [PATCH 073/128] Added mul support. Fixed SLLIW --- src/simulator/print.rs | 47 +++++++++++++++++++++++++++++++++++------- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 6e18925..451d3ef 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -5,7 +5,7 @@ use super::global::*; const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; -const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; +const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"]; const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"]; const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; @@ -13,7 +13,7 @@ const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; // Register name mapping -const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", // fp ou s0 ? +const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"]; @@ -95,10 +95,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } else { format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } - } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{},{},{}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) + format!("{}\t{},{},0x{:x}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_OPW => { @@ -216,8 +214,8 @@ mod test { let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); - assert_eq!("addiw\tt3,a7,0", print::print(addiw, 0)); - assert_eq!("slli\tt3,a7,a6", print::print(slliw, 0)); + assert_eq!("addiw\tt3,a7,0x0", print::print(addiw, 0)); + assert_eq!("slliw\tt3,a7,0x10", print::print(slliw, 0)); assert_eq!("srai\tt3,a7,17", print::print(srai, 0)); } @@ -259,7 +257,10 @@ mod test { assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); - //Waiting for mulw implementation assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); + + //Waiting for mulw implementation + assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); @@ -286,4 +287,34 @@ mod test { assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); } + #[test] + fn test_mul_prog() { + assert_eq!("addi sp,sp,-32", print::print(decode::decode(0xfe010113), 0)); + assert_eq!("sd s0,24(sp)", print::print(decode::decode(0x00813c23), 0)); + assert_eq!("addi s0,sp,32", print::print(decode::decode(0x02010413), 0)); + assert_eq!("addi a5,zero,5", print::print(decode::decode(0x00500793), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); + assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("addi a5,a4,0", print::print(decode::decode(0x00070793), 0)); + assert_eq!("slliw a5,a5,0x2", print::print(decode::decode(0x0027979b), 0)); + assert_eq!("addw a5,a5,a4", print::print(decode::decode(0x00e787bb), 0)); + assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0)); + assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); + assert_eq!("sw a5,-28(s0)", print::print(decode::decode(0xfef42223), 0)); + assert_eq!("lw a5,-28(s0)", print::print(decode::decode(0xfe442783), 0)); + assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); + assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); + assert_eq!("divw a5,a4,a5", print::print(decode::decode(0x02f747bb), 0)); + assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); + assert_eq!("addi a5,zero,0", print::print(decode::decode(0x00000793), 0)); + assert_eq!("addi a0,a5,0", print::print(decode::decode(0x00078513), 0)); + assert_eq!("ld s0,24(sp)", print::print(decode::decode(0x01813403), 0)); + assert_eq!("addi sp,sp,32", print::print(decode::decode(0x02010113), 0)); + assert_eq!("jalr zero,0(ra)", print::print(decode::decode(0x00008067), 0)); + } + } \ No newline at end of file From f8a7607ea8951d9166849393d93b29035a37fea0 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 01:17:46 +0100 Subject: [PATCH 074/128] conversion + creation MemChecker from a file path --- src/simulator/mem_cmp.rs | 105 +++++++++++++++++++++++++++++++++++---- test_file_section.txt | 8 +++ 2 files changed, 102 insertions(+), 11 deletions(-) create mode 100644 test_file_section.txt diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 859bfad..02a3602 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -1,6 +1,15 @@ +use std::fs; +use std::io; +use std::io::BufRead; + + + /* TRUCS MANQUANT * Verifier qu'il y a un nombre pair de caractere hexa dans la ligne correspondante d'une section du fichier source * Sinon on ne peut pas automatiquement remplir chaque octect car 2 hexa = 1 octet + + +* OUBLI CONVERSIONS ADDR ET LEN QUI SONT AUSSI EN CARACTÈRES HEXA DS LE FICHIER */ @@ -41,10 +50,12 @@ struct Section{ * Voir si instanciation d'une structure deplace les valeurs "locales" à la méthode from, je sais plus .... */ impl Section{ + fn from(section: &SectionFormat) -> Section { + let mut content: Vec = Vec::new(); - let addr: usize = section.addr.parse().unwrap(); - let len: usize = section.len.parse().unwrap(); + let addr: usize = string_hex_to_usize(§ion.addr); + let len: usize = string_hex_to_usize(§ion.len); let mut tmp_a: char = ' '; let mut tmp_b: char = ' '; @@ -60,7 +71,6 @@ impl Section{ } } - Section{addr:addr, len:len, content:content} } } @@ -76,12 +86,51 @@ struct Mem_Checker{ impl Mem_Checker{ - /*fn from(path: &String) -> Mem_Checker{ + fn from(path: &String) /*-> Mem_Checker*/{ - }*/ + let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); + let reader = io::BufReader::new(file); + let mut pc: usize = 0; + let mut sp: usize = 0; + + for (i,line) in reader.lines().enumerate() { + + let current_line = line.unwrap(); + + if i == 0 { + //Lecture de PC + pc = string_hex_to_usize(¤t_line); + } + else if i == 1 { + //Lecture SP + sp = string_hex_to_usize(¤t_line); + } + else { + //Lecture des sections + } + } + } } + +fn string_hex_to_usize(s: &String) -> usize{ + + let max_pow = (s.len()-1) as u32; + let mut ret_value: usize = 0; + let base: usize = 16; + + for (i,c )in s.chars().enumerate(){ + print!("Current char :: {} :: Current pow :: {} ::", c, max_pow - (i as u32)); + let tmp: usize = (one_hex_to_dec(c) as usize); + ret_value += base.pow(max_pow - (i as u32))*tmp; + } + + return ret_value; +} + + + /* * c doit etre un caractère hexadécimale */ @@ -101,7 +150,7 @@ fn one_hex_to_dec(c: char) -> u8 { } } - + fn two_hex_to_u8(c1: char, c2: char) -> u8 { let a = one_hex_to_dec(c1); @@ -110,10 +159,49 @@ fn two_hex_to_u8(c1: char, c2: char) -> u8 { 16*a + b } + + +/* +* Juste pour voir si via BufReader les \n sont présent, apres test il s'avère que non +* De toute facon on limitera d'une section la lecture par len + */ +fn test_show_sections_file(){ + let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); + let reader = io::BufReader::new(file); + + for line in reader.lines() { + //println!("Tailles de la ligne : {}", + let current = line.unwrap(); + //println!("Taille de la ligne : {}", current.len()); // En effet pas de \n dans chaque line, parfait + println!("{}", ¤t); + } + +} + + + + #[cfg(test)] mod tests { use super::*; + + #[test] + fn test_string_hex_to_usize(){ + let s = String::from("AE1F20"); + //println!("taille de string : {}", s.len()); + let expected: usize = 11411232; + let result = string_hex_to_usize(&s); + + assert_eq!(expected,result); + } + + #[test] + fn tmp_fct_read_file(){ + println!("Reading A file \n"); + test_show_sections_file(); + } + #[test] fn test_create_section_content(){ let section_format = SectionFormat{ @@ -136,11 +224,6 @@ mod tests { assert_eq!(section.content, expected_vec); } - - - - - #[test] fn test_mod(){ let cond = (0%2) == 0; diff --git a/test_file_section.txt b/test_file_section.txt new file mode 100644 index 0000000..7198c00 --- /dev/null +++ b/test_file_section.txt @@ -0,0 +1,8 @@ +0 +0 +0 0 +F4A12200 +0 0 +01022B +0 0 +FFACBC5CEF From 6945128f720da30ef460ac0ee1a031d3eeb0fb26 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 12:37:21 +0100 Subject: [PATCH 075/128] test create mem check --- src/simulator/mem_cmp.rs | 54 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 02a3602..00a60eb 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -73,6 +73,13 @@ impl Section{ Section{addr:addr, len:len, content:content} } + + + fn print_Section(s: &Section){ + println!("ADDR :: {}", s.addr); + println!("LEN :: {}", s.len); + println!("CONTENT :: {:?}", s.content); + } } /* @@ -86,12 +93,18 @@ struct Mem_Checker{ impl Mem_Checker{ - fn from(path: &String) /*-> Mem_Checker*/{ + + fn from(path: &String) -> Mem_Checker { let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); let reader = io::BufReader::new(file); + let mut pc: usize = 0; let mut sp: usize = 0; + let mut sections: Vec
= Vec::new(); + + let mut tmp_addr_str: String = String::new(); + let mut tmp_len_str: String = String::new(); for (i,line) in reader.lines().enumerate() { @@ -107,8 +120,38 @@ impl Mem_Checker{ } else { //Lecture des sections + if current_line.contains(' ') { + //lecture ligne ADDR LEN + let next_word_index = current_line.find(' ').unwrap(); + tmp_addr_str = String::from(¤t_line[0..next_word_index]); + tmp_len_str = String::from(¤t_line[next_word_index+1..]); + } + else { + //lecture ligne CONTENT + let section_f = SectionFormat{ + addr: tmp_addr_str.clone(), + len: tmp_len_str.clone(), + content: current_line, + }; + sections.push(Section::from(§ion_f)); + } + } } + + Mem_Checker{pc:pc, sp:sp, sections:sections} + } + + + fn print_Mem_Checker(m_c: &Mem_Checker){ + println!("PC :: {}", m_c.pc); + println!("SP :: {}", m_c.sp); + + for(i,s) in m_c.sections.iter().enumerate() { + println!("\nSection {}\n", i); + Section::print_Section(&s); + } + } } @@ -121,7 +164,7 @@ fn string_hex_to_usize(s: &String) -> usize{ let base: usize = 16; for (i,c )in s.chars().enumerate(){ - print!("Current char :: {} :: Current pow :: {} ::", c, max_pow - (i as u32)); + //println!("Current char :: {} :: Current pow :: {} ::", c, max_pow - (i as u32)); let tmp: usize = (one_hex_to_dec(c) as usize); ret_value += base.pow(max_pow - (i as u32))*tmp; } @@ -185,6 +228,13 @@ fn test_show_sections_file(){ mod tests { use super::*; + #[test] + fn test_create_Mem_Chercker(){ + let path: String = "osef".to_string(); + let m_c = Mem_Checker::from(&path); + Mem_Checker::print_Mem_Checker(&m_c); + } + #[test] fn test_string_hex_to_usize(){ From 5d7b35b9e63bd9cda25b52d3032ed0dfb3d253bc Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 12:45:39 +0100 Subject: [PATCH 076/128] print mem checker --- test_file_section.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test_file_section.txt b/test_file_section.txt index 7198c00..05d3ead 100644 --- a/test_file_section.txt +++ b/test_file_section.txt @@ -1,8 +1,8 @@ 0 0 -0 0 +FF FF F4A12200 -0 0 +A0 0A 01022B -0 0 +0B 0F FFACBC5CEF From 027e91119bb53d3261bca402654d0e510f84c563 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 14:34:09 +0100 Subject: [PATCH 077/128] waiting for machine update --- src/simulator/machine.rs | 3 +++ src/simulator/mem_cmp.rs | 32 ++++++++++++++++++++++++++++++++ src/simulator/mod.rs | 2 +- 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 44888f4..1624713 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -2,6 +2,7 @@ use std::ops::{Add, Sub}; use super::{decode::{Instruction, decode}}; use super::global::*; + /// doit disparaitre const MEM_SIZE : usize = 4096; @@ -11,6 +12,8 @@ impl RegisterNum for i64 {} impl RegisterNum for f32 {} + + pub struct Register { register: [U; 32] } diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 00a60eb..9f2e160 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -2,6 +2,8 @@ use std::fs; use std::io; use std::io::BufRead; +const MEM_SIZE : usize = 4096; + /* TRUCS MANQUANT @@ -153,6 +155,36 @@ impl Mem_Checker{ } } + + fn Mem_Checker_check(m_c: &Mem_Checker, memory: [u8 ; MEM_SIZE]){ + /* + * Check pc, sp + */ + + + /* + * Check sections + */ + + for(i, s) in m_c.sections.iter().enumerate() { + let addr = s.addr; + let len = s.len; + let segment = &s.content; + + /* + regarder dans mem[addr] + a cette adresse verifier len octets + */ + + for j in 0..(len-1){ + if segment[j] != memory[addr + j] { + println!("missmatch"); + } + } + + } + + } } diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 76c2931..54d271e 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -1,7 +1,7 @@ pub mod machine; pub mod decode; pub mod print; -mod mem_cmp; +pub mod mem_cmp; pub mod global { From 5af3a7e7382ceae6f8437b08576655db371566df Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 8 Feb 2023 14:46:56 +0100 Subject: [PATCH 078/128] Remove instructions in favor of memory --- src/simulator/machine.rs | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 44888f4..887a297 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -58,9 +58,9 @@ impl Register { pub struct Machine { pub pc : u64, + pub sp: usize, pub int_reg : Register, pub fp_reg : Register, - pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; @@ -80,12 +80,9 @@ impl Machine { value >>= 1; } - // let int_reg = Register::::init(); - // let fp_reg = Register::::init(); - Machine { pc : 0, - instructions : [0 ; 100], + sp: 0, int_reg : Register::::init(), fp_reg : Register::::init(), main_memory : [0 ; MEM_SIZE], @@ -167,12 +164,17 @@ impl Machine { float localFloat; uint64_t value;*/ - if machine.instructions.len() <= machine.pc as usize { + if machine.main_memory.len() <= machine.pc as usize { println!("ERROR : number max of instructions rushed"); return ; } + let mut val: [u8; 8] = [0; 8]; + for i in 0..8 { + val[i] = machine.main_memory[machine.pc as usize + i]; + } - let inst : Instruction = decode(machine.instructions[machine.pc as usize]); + let val = u64::from_le_bytes(val); + let inst : Instruction = decode(val); match inst.opcode { @@ -588,7 +590,7 @@ impl Machine { _ => { panic!("{} opcode non géré", inst.opcode)}, } - machine.pc += 4; + machine.pc += 8; } } From 8b84dee271eee8535a1d99c1f3be035e614f1f08 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 8 Feb 2023 15:05:02 +0100 Subject: [PATCH 079/128] pc - 8 in one instruction --- src/simulator/machine.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index f8d3aed..dbd18bb 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -185,11 +185,11 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); }, RISCV_AUIPC => { - machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); + machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64); }, RISCV_JAL => { machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); - machine.pc += inst.imm21_1_signed as u64 - 4; + machine.pc += inst.imm21_1_signed as u64 - 8; }, RISCV_JALR => { let tmp = machine.pc; @@ -203,32 +203,32 @@ impl Machine { match inst.funct3 { RISCV_BR_BEQ => { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, RISCV_BR_BNE => { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, RISCV_BR_BLT => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, RISCV_BR_BGE => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, RISCV_BR_BLTU => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, RISCV_BR_BGEU => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc += inst.imm13_signed as u64 - 8; } }, _ => { From 297a4d1d0a04ed14b684ca004b2f6705e543016d Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 15:50:14 +0100 Subject: [PATCH 080/128] memory context load --- src/simulator/mem_cmp.rs | 81 ++++++++++++++++++++++++++++------------ 1 file changed, 57 insertions(+), 24 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 9f2e160..27b3795 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -1,6 +1,7 @@ use std::fs; use std::io; use std::io::BufRead; +use crate::Machine; const MEM_SIZE : usize = 4096; @@ -156,35 +157,43 @@ impl Mem_Checker{ } - fn Mem_Checker_check(m_c: &Mem_Checker, memory: [u8 ; MEM_SIZE]){ - /* - * Check pc, sp - */ + fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ + + machine.sp = m_c.sp; + machine.pc = m_c.pc as u64; - /* - * Check sections - */ - - for(i, s) in m_c.sections.iter().enumerate() { - let addr = s.addr; - let len = s.len; - let segment = &s.content; - - /* - regarder dans mem[addr] - a cette adresse verifier len octets - */ - - for j in 0..(len-1){ - if segment[j] != memory[addr + j] { - println!("missmatch"); - } + for section in m_c.sections.iter() { + + for (i,b) in section.content.iter().enumerate() { + machine.main_memory[section.addr + i] = *b; } + } + } - } + + /* + * FOR DEBUG + */ + fn compare_print_m_c_machine(m_c: &Mem_Checker, machine: &mut Machine){ + + Mem_Checker::print_Mem_Checker(m_c); + + for section in m_c.sections.iter() { + + print!("\n\n"); + + println!("Content addr : {}", section.addr); + println!("Content len (number of bytes) : {}", section.len); + + for i in 0..section.len { + println!("mem[{}] = {}", section.addr + i, machine.main_memory[section.addr + i]); + } + } } + + } @@ -261,7 +270,31 @@ mod tests { use super::*; #[test] - fn test_create_Mem_Chercker(){ + fn test_fill_memory(){ + let path = "osef".to_string(); + let m_c = Mem_Checker::from(&path); + let mut machine = Machine::_init_machine(); + + Mem_Checker::fill_memory_from_Mem_Checker(&m_c, &mut machine); + + print!("\n Comparing memory from loaded context\n\n"); + + Mem_Checker::compare_print_m_c_machine(&m_c, &mut machine); + + } + + + #[test] + fn test_enum_start_at_zero(){ + let v = vec![1,2,3]; + + for (i,val) in v.iter().enumerate() { + println!("i = {} :: v[i] = {}", i, val); + } + } + + #[test] + fn test_create_Mem_Checker(){ let path: String = "osef".to_string(); let m_c = Mem_Checker::from(&path); Mem_Checker::print_Mem_Checker(&m_c); From 54a20296f9b255226cf510734872bff825c0b3a7 Mon Sep 17 00:00:00 2001 From: Moysan Gabriel Date: Wed, 8 Feb 2023 15:51:55 +0100 Subject: [PATCH 081/128] bruh --- src/simulator/mem_cmp.rs | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 27b3795..723eef7 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -7,17 +7,11 @@ const MEM_SIZE : usize = 4096; -/* TRUCS MANQUANT +/* TRUCS MANQUANTS * Verifier qu'il y a un nombre pair de caractere hexa dans la ligne correspondante d'une section du fichier source * Sinon on ne peut pas automatiquement remplir chaque octect car 2 hexa = 1 octet - - -* OUBLI CONVERSIONS ADDR ET LEN QUI SONT AUSSI EN CARACTÈRES HEXA DS LE FICHIER */ - - - /* FORMAT FICHIER.TXT Représentant la mémoire apres éxecution d'un prog * PC * SP @@ -380,4 +374,4 @@ mod tests { let b = two_hex_to_u8('A', '5'); assert_eq!(165u8, b); } -} \ No newline at end of file +} From fe930e4a0dbb66c9ce6e3211173ec050dd0b7c39 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Feb 2023 15:01:41 +0000 Subject: [PATCH 082/128] ONGOING: Test programs --- test_programs/Makefile | 14 ++++++++++ test_programs/Makefile.config | 18 ++++++++++++ test_programs/Makefile.objdumps | 24 ++++++++++++++++ test_programs/README.md | 28 +++++++++++++++++++ test_programs/riscv_instructions/Makefile | 2 ++ .../boolean_logic/comparisons.c | 15 ++++++++++ .../riscv_instructions/boolean_logic/if.c | 10 +++++++ .../riscv_instructions/boolean_logic/switch.c | 7 +++++ .../jump_instructions/jump.c | 7 +++++ .../jump_instructions/ret.c | 3 ++ .../simple_arithmerics/README.md | 15 ++++++++++ .../simple_arithmerics/unsigned_addition.c | 6 ++++ .../simple_arithmerics/unsigned_division.c | 6 ++++ .../unsigned_multiplication.c | 6 ++++ .../unsigned_substraction.c | 6 ++++ 15 files changed, 167 insertions(+) create mode 100644 test_programs/Makefile create mode 100644 test_programs/Makefile.config create mode 100644 test_programs/Makefile.objdumps create mode 100644 test_programs/README.md create mode 100644 test_programs/riscv_instructions/Makefile create mode 100644 test_programs/riscv_instructions/boolean_logic/comparisons.c create mode 100644 test_programs/riscv_instructions/boolean_logic/if.c create mode 100644 test_programs/riscv_instructions/boolean_logic/switch.c create mode 100644 test_programs/riscv_instructions/jump_instructions/jump.c create mode 100644 test_programs/riscv_instructions/jump_instructions/ret.c create mode 100644 test_programs/riscv_instructions/simple_arithmerics/README.md create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c diff --git a/test_programs/Makefile b/test_programs/Makefile new file mode 100644 index 0000000..e15867e --- /dev/null +++ b/test_programs/Makefile @@ -0,0 +1,14 @@ +TOPDIR=. +include $(TOPDIR)/Makefile.config + +# +# Main targets +# +objdumps: + $(MAKE) -C riscv_instructions + +programs: + $(MAKE) -C programs + +clean: + rm -rf $(TOPDIR)/target \ No newline at end of file diff --git a/test_programs/Makefile.config b/test_programs/Makefile.config new file mode 100644 index 0000000..fca5849 --- /dev/null +++ b/test_programs/Makefile.config @@ -0,0 +1,18 @@ +# This is part of a GNU -*- Makefile -*-, to specify system-dependent +# parts of the Makefile enviroment. +# +# This gets included as part of the GNU-Makefile used in each of +# the subdirectories. +# +# Depending on your platform, you need to select the correct definition. + +## RISCV target compilation toolchain +RISCV_PREFIX=/opt/riscv/bin/ +RISCV_AS = $(RISCV_PREFIX)riscv64-unknown-elf-gcc -x assembler-with-cpp -march=rv64imfd +RISCV_GCC = $(RISCV_PREFIX)riscv64-unknown-elf-gcc +RISCV_LD = $(RISCV_PREFIX)riscv64-unknown-elf-ld +RISCV_OBJDUMP = $(RISCV_PREFIX)riscv64-unknown-elf-objdump +RISCV_ASFLAGS = $(RISCV_CPPFLAGS) +RISCV_CPPFLAGS = #nil +RISCV_CFLAGS = -Wall $(RISCV_CPPFLAGS) -march=rv64imfd +RISCV_LDFLAGS = #nil diff --git a/test_programs/Makefile.objdumps b/test_programs/Makefile.objdumps new file mode 100644 index 0000000..78a4520 --- /dev/null +++ b/test_programs/Makefile.objdumps @@ -0,0 +1,24 @@ +include $(TOPDIR)/Makefile.config + +COVERAGE = $(TOPDIR)/riscv_instructions + +AS = $(RISCV_AS) -c +GCC = $(RISCV_GCC) +LD = $(RISCV_LD) + +INCPATH += -I$(TOPDIR) -I$(COVERAGE) +ASFLAGS = $(RISCV_ASFLAGS) $(INCPATH) +CFLAGS = $(RISCV_CFLAGS) $(INCPATH) + +# Rules +%.a: + $(AR) rcv $@ $^ + +%.o: %.c + $(GCC) $(CFLAGS) -c $< + +%.o: %.s + $(AS) $(ASFLAGS) -c $< + +$(PROGRAMS): + $(LD) $+ -o $@ \ No newline at end of file diff --git a/test_programs/README.md b/test_programs/README.md new file mode 100644 index 0000000..6e73dba --- /dev/null +++ b/test_programs/README.md @@ -0,0 +1,28 @@ +# BurritOS Test programs +This folder contains small C programs pertaining to the assessment of the correctness of BurritOS' behavior. + +## Folder Structure + - **riscv_instructions**: contains small programs for testing simulator instruction coverage. + +## How to build +### In the Makefile.config file +Set the variables to the correct paths for the [RISCV Newlib compilation toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain). Simply changing the `RISCV_PREFIX` variable should do the trick. **Do not forget to add a trailing slash**. + +### Exporting objdumps + +``` +$ make objdumps +``` + +### Compiling programs +``` +$ make programs +``` + +### Cleaning +``` +$ make clean +``` + +### Output folder +Compilation results are located in the target/objdumps and target/programs directories. \ No newline at end of file diff --git a/test_programs/riscv_instructions/Makefile b/test_programs/riscv_instructions/Makefile new file mode 100644 index 0000000..29df4bd --- /dev/null +++ b/test_programs/riscv_instructions/Makefile @@ -0,0 +1,2 @@ +TOPDIR = ../ +include $(TOPDIR)/Makefile.objdumps diff --git a/test_programs/riscv_instructions/boolean_logic/comparisons.c b/test_programs/riscv_instructions/boolean_logic/comparisons.c new file mode 100644 index 0000000..f653fff --- /dev/null +++ b/test_programs/riscv_instructions/boolean_logic/comparisons.c @@ -0,0 +1,15 @@ +int main() { + int x = 0; + int y = 1; + while (x <= y) { + if (x > y) { + x += 1; + } else if (x == y) { + x += y; + } else if (x < y) { + y += 1; + } else { + return; + } + } +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/boolean_logic/if.c b/test_programs/riscv_instructions/boolean_logic/if.c new file mode 100644 index 0000000..2a11b58 --- /dev/null +++ b/test_programs/riscv_instructions/boolean_logic/if.c @@ -0,0 +1,10 @@ +int main() { + int x = 1; + if (x == 1 && x > 0) { + x = 2; + } else if (x || x == 0 ) { + x = 3; + } else { + x = 0; + } +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/boolean_logic/switch.c b/test_programs/riscv_instructions/boolean_logic/switch.c new file mode 100644 index 0000000..86a181c --- /dev/null +++ b/test_programs/riscv_instructions/boolean_logic/switch.c @@ -0,0 +1,7 @@ +int main() { + int x = 0; + switch(1) { + case 1: x = 1; break; + default: return; + } +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/jump_instructions/jump.c b/test_programs/riscv_instructions/jump_instructions/jump.c new file mode 100644 index 0000000..c4fd641 --- /dev/null +++ b/test_programs/riscv_instructions/jump_instructions/jump.c @@ -0,0 +1,7 @@ +int test() { + return 1; +} + +int main() { + int x = test(); +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/jump_instructions/ret.c b/test_programs/riscv_instructions/jump_instructions/ret.c new file mode 100644 index 0000000..84eb8ea --- /dev/null +++ b/test_programs/riscv_instructions/jump_instructions/ret.c @@ -0,0 +1,3 @@ +int main() { + return 1; +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/README.md b/test_programs/riscv_instructions/simple_arithmerics/README.md new file mode 100644 index 0000000..031c1be --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/README.md @@ -0,0 +1,15 @@ +# Simple arithmetics program + +These allow to check whether the following instructions are correctly implemented. + +- addi +- sd +- sw +- li +- sw +- lw +- mv +- addw +- nop +- ld +- ret \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c new file mode 100644 index 0000000..2881ac7 --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c @@ -0,0 +1,6 @@ +// EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 1 +void main() { + unsigned int x = 0; + unsigned int y = 1; + x = x + y; +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c b/test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c new file mode 100644 index 0000000..729f889 --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c @@ -0,0 +1,6 @@ +// Expecting two variables with a value of two +void main() { + unsigned int x = 4; + unsigned int y = 2; + x = x / y; +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c b/test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c new file mode 100644 index 0000000..c79294d --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c @@ -0,0 +1,6 @@ +// EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 2 +void main() { + unsigned int x = 1; + unsigned int y = 2; + x = x * y; +} \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c b/test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c new file mode 100644 index 0000000..dd4e09b --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c @@ -0,0 +1,6 @@ +// EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 1 +void main() { + unsigned int x = 1; + unsigned int y = 1; + x = x - y; +} \ No newline at end of file From 3269fa353f6057dc1153017ce6ab486b1a19831b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Mon, 13 Feb 2023 11:08:24 +0100 Subject: [PATCH 083/128] Implemented extract_memory --- src/simulator/machine.rs | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index dbd18bb..f3f635b 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -1,7 +1,8 @@ -use std::ops::{Add, Sub}; +use std::{ops::{Add, Sub}, io::Write}; use super::{decode::{Instruction, decode}}; use super::global::*; +use std::fs::File; /// doit disparaitre const MEM_SIZE : usize = 4096; @@ -136,6 +137,17 @@ impl Machine { } } + /// Write the contains of the main memory of the machine + /// in a file called burritos_memory.txt + /// + /// ### Parameters + /// + /// - **machine** contains the memory + pub fn extract_memory(machine: &mut Machine){ + let mut file = File::create("burritos_memory.txt").unwrap(); + file.write(&machine.main_memory); + } + /// Execute the instructions table of a machine putted in param /// /// ### Parameters From e3c6917486663e531395fb52333822f22d374b91 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 15 Feb 2023 13:55:16 +0100 Subject: [PATCH 084/128] Added RV32F Standard Extension --- src/simulator/print.rs | 108 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 103 insertions(+), 5 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 451d3ef..0567fef 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -1,5 +1,4 @@ #![allow(dead_code)] -#![allow(unused_variables)] use super::decode::{Instruction}; use super::global::*; @@ -12,6 +11,7 @@ const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; + // Register name mapping const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", @@ -28,6 +28,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 let rd = ins.rd as usize; let rs1 = ins.rs1 as usize; let rs2 = ins.rs2 as usize; + let rs3 = ins.rs3 as usize; match ins.opcode { RISCV_OP => { @@ -118,6 +119,104 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("{}\t{},{},{}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } }, + // RV32F Standard Extension + RISCV_FLW => { + format!("flw\t{},{},({})", REG_F[rd], ins.imm12_I_signed, REG_F[rs1]) + }, + RISCV_FSW => { + format!("fsw\t{},{},({})", REG_F[rs2], "OFFSET TODO", REG_F[rs1]) // TODO Offset in decode + }, + RISCV_FMADD => { + format!("fmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3]) + }, + RISCV_FMSUB => { + format!("fmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3]) + }, + RISCV_FNMSUB => { + format!("fnmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3]) + }, + RISCV_FNMADD => { + format!("fnmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3]) + }, + RISCV_FP => { + let name: &str; + match ins.funct7 { + RISCV_FP_ADD => { + name = "fadd"; + }, + RISCV_FP_SUB => { + name = "fsub"; + }, + RISCV_FP_MUL => { + name = "fmul"; + }, + RISCV_FP_DIV => { + name = "fdiv"; + }, + RISCV_FP_SQRT => { + name = "fsqrt"; + }, + RISCV_FP_FSGN => { + + match ins.funct3 { + RISCV_FP_FSGN_J => { + name = "fsgnj"; + }, + RISCV_FP_FSGN_JN => { + name = "fsgnn"; + }, + RISCV_FP_FSGN_JX => { + name = "fsgnx"; + }, + _ => name = "fsgn" + } + }, + RISCV_FP_MINMAX => { + if ins.funct3 == 0 { + name = "fmin"; + } else { + name = "fmax"; + } + }, + RISCV_FP_FCVTW => { + if rs2 == 0 { + name = "fcvt.w.s"; + } else { + name = "fcvt.wu.s"; + } + + }, + RISCV_FP_FMVXFCLASS => { + if ins.funct3 == 0 { + name = "fmv.x.w"; + } else { + name = "fclass.s"; + } + }, + RISCV_FP_FCMP => { + if ins.funct3 == 0 { + name = "fle.s"; + } else if ins.funct3 == 1 { + name = "flt.s"; + } else { + name = "feq.s"; + } + }, + RISCV_FP_FCVTS => { + if rs2 == 0 { + name = "fcvt.s.w" + } else { + name = "fcvt.s.wu" + } + }, + RISCV_FP_FMVW => { + name = "fmv.w.x"; + }, + _ => name = "todo" + } + format!("{}\t{}{}{}", name, REG_F[rd], REG_F[rs1], REG_F[rs2]) + }, + RISCV_SYSTEM => { "ecall".to_string() }, @@ -226,10 +325,12 @@ mod test { let bne: decode::Instruction = decode::decode(0b0000000_10000_10001_001_00000_1100011); let blt: decode::Instruction = decode::decode(0b0000000_10000_10001_100_00000_1100011); let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); + let bge2: decode::Instruction = decode::decode(0x00f75863); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); assert_eq!("blt\ta7,a6,0", print::print(blt, 0)); assert_eq!("bge\ta7,a6,0", print::print(bge, 0)); + assert_eq!("bge\ta4,a5,104d4", print::print(bge2, 0x104c4)); assert_eq!("bltu\ta7,a6,0", print::print(bltu, 0)); assert_eq!("bgeu\ta7,a6,0", print::print(bgeu, 0)); assert_eq!("bne\ta7,a6,0", print::print(bne, 0)); @@ -257,10 +358,7 @@ mod test { assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0)); - - //Waiting for mulw implementation - assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); - + assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0)); assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0)); assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0)); assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0)); From d76047e48b7d35bc36112f98819a1d3326c4092c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 15 Feb 2023 14:22:31 +0100 Subject: [PATCH 085/128] changed Mem_Checker method --- src/simulator/mem_cmp.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 723eef7..abddae9 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -107,11 +107,11 @@ impl Mem_Checker{ let current_line = line.unwrap(); - if i == 0 { + if i == current_line.len()-2 { //Lecture de PC pc = string_hex_to_usize(¤t_line); } - else if i == 1 { + else if i == current_line.len()-1 { //Lecture SP sp = string_hex_to_usize(¤t_line); } From 06f0be9ecea4ff4335aa048dee04940b1b288dea Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 15 Feb 2023 14:33:40 +0100 Subject: [PATCH 086/128] Fixed R32F --- src/simulator/print.rs | 47 ++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 0567fef..4cf103b 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -142,79 +142,76 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 let name: &str; match ins.funct7 { RISCV_FP_ADD => { - name = "fadd"; + format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_SUB => { - name = "fsub"; + format!("{}\t{}{}{}", "fsub.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_MUL => { - name = "fmul"; + format!("{}\t{}{}{}", "fmul.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_DIV => { - name = "fdiv"; + format!("{}\t{}{}{}", "fdiv.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_SQRT => { - name = "fsqrt"; + format!("{}\t{}{}", "fsqrt.s", REG_F[rd], REG_F[rs1]) }, RISCV_FP_FSGN => { - match ins.funct3 { RISCV_FP_FSGN_J => { - name = "fsgnj"; + format!("{}\t{}{}{}", "fsgnj.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_FSGN_JN => { - name = "fsgnn"; + format!("{}\t{}{}{}", "fsgnn.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_FP_FSGN_JX => { - name = "fsgnx"; + format!("{}\t{}{}{}", "fsgnx.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) }, - _ => name = "fsgn" + _ => todo!("Unknown code") } }, RISCV_FP_MINMAX => { if ins.funct3 == 0 { - name = "fmin"; + format!("{}\t{}{}{}", "fmin.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) } else { - name = "fmax"; + format!("{}\t{}{}{}", "fmax.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) } }, RISCV_FP_FCVTW => { if rs2 == 0 { - name = "fcvt.w.s"; + format!("{}\t{}{}", "fcvt.w.s", REG_F[rd], REG_F[rs1]) } else { - name = "fcvt.wu.s"; + format!("{}\t{}{}", "fcvt.wu.s", REG_F[rd], REG_F[rs1]) } - }, RISCV_FP_FMVXFCLASS => { if ins.funct3 == 0 { - name = "fmv.x.w"; + format!("{}\t{}{}", "fmv.x.w", REG_F[rd], REG_F[rs1]) } else { - name = "fclass.s"; + format!("{}\t{}{}", "fclass.s", REG_F[rd], REG_F[rs1]) } }, RISCV_FP_FCMP => { if ins.funct3 == 0 { - name = "fle.s"; + format!("{}\t{}{}{}", "fle.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) } else if ins.funct3 == 1 { - name = "flt.s"; + format!("{}\t{}{}{}", "flt.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) } else { - name = "feq.s"; + format!("{}\t{}{}{}", "feq.s", REG_F[rd], REG_F[rs1], REG_F[rs2]) } }, RISCV_FP_FCVTS => { if rs2 == 0 { - name = "fcvt.s.w" + format!("{}\t{}{}", "fcvt.s.w", REG_F[rd], REG_F[rs1]) } else { - name = "fcvt.s.wu" + format!("{}\t{}{}", "fcvt.s.wu", REG_F[rd], REG_F[rs1]) } }, RISCV_FP_FMVW => { - name = "fmv.w.x"; + format!("{}\t{}{}", "fmv.w.x", REG_F[rd], REG_F[rs1]) }, - _ => name = "todo" + _ => todo!("Unknown code") } - format!("{}\t{}{}{}", name, REG_F[rd], REG_F[rs1], REG_F[rs2]) }, RISCV_SYSTEM => { From 4425ac747e650fe4cb3ae03865160cb5f09123b1 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 15 Feb 2023 15:45:37 +0100 Subject: [PATCH 087/128] debuging mem_checker::from --- src/simulator/mem_cmp.rs | 12 +++++---- test_file_section.txt | 23 ++++++++++++------ .../simple_arithmerics/unsigned_addition.o | Bin 0 -> 1088 bytes 3 files changed, 22 insertions(+), 13 deletions(-) create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index abddae9..c4a8a5a 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -94,7 +94,10 @@ impl Mem_Checker{ fn from(path: &String) -> Mem_Checker { let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); - let reader = io::BufReader::new(file); + let reader = io::BufReader::new(&file); + let reader2 = io::BufReader::new(&file); + let lines = reader.lines(); + let length = reader2.lines().count(); let mut pc: usize = 0; let mut sp: usize = 0; @@ -103,15 +106,15 @@ impl Mem_Checker{ let mut tmp_addr_str: String = String::new(); let mut tmp_len_str: String = String::new(); - for (i,line) in reader.lines().enumerate() { + for (i,line) in lines.enumerate() { let current_line = line.unwrap(); - if i == current_line.len()-2 { + if i == length-2 { //Lecture de PC pc = string_hex_to_usize(¤t_line); } - else if i == current_line.len()-1 { + else if i == length-1 { //Lecture SP sp = string_hex_to_usize(¤t_line); } @@ -277,7 +280,6 @@ mod tests { } - #[test] fn test_enum_start_at_zero(){ let v = vec![1,2,3]; diff --git a/test_file_section.txt b/test_file_section.txt index 05d3ead..df1b0d2 100644 --- a/test_file_section.txt +++ b/test_file_section.txt @@ -1,8 +1,15 @@ -0 -0 -FF FF -F4A12200 -A0 0A -01022B -0B 0F -FFACBC5CEF +addi sp,sp,-32 +sd s0,24(sp) +addi s0,sp,32 +sw zero,-20(s0) +li a5,1 +sw a5,-24(s0) +lw a5,-20(s0) +mv a4,a5 +lw a5,-24(s0) +addw a5,a4,a5 +sw a5,-20(s0) +nop +ld s0,24(sp) +addi sp,sp,32 +ret \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o new file mode 100644 index 0000000000000000000000000000000000000000..3d69445f952a67be3ab705cbfff4767457813b8b GIT binary patch literal 1088 zcmbtTPfG$(5TE^H>dlfOs6bJ)ARen}M0hZyy!0Jp)y4L(tGG`w2uck40A2hdow{`B zL-aKwq1)CxdoLd^>EgidZ{|1id-G=4y*g?AqtcHefS*xgiLN0CQ)aU#u{q$&K(BzTJ1Eo-zhpy z*(n`aR^j9zRVb1ovEVF)`Mw*phM;YsYbGN7;c>|=_N<17FQoo8HiHT8U(1S&F4UDh7Vwc6_JZu-k2yx?P{NAUgujc6|U6 zTzk}RBGUd3UI~vnBMPK#QyWM#2!OP@p6B?;&9_NxO8aheK%GEzS_yYh&9<szKHD3M2@Ol;0jpwl-wu1f;wd_pwgA)CBF(;eoFR+YByn9csVg8g8X(b_a zf@ZPwYY7@&xc9~}ipb_<4>R`NFpJ}(?vC+O-e`{nlBxaIF}FpF literal 0 HcmV?d00001 From 9fab99e31f39d73df97ddd4f5e4ef4a9e58051da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 15 Feb 2023 16:14:27 +0100 Subject: [PATCH 088/128] make struct and function public --- src/simulator/mem_cmp.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index abddae9..3e2ccd6 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -82,7 +82,7 @@ impl Section{ /* * Representation de l'etat de la mémoire (apres execution.... a confirmer), sous forme de sections */ -struct Mem_Checker{ +pub struct Mem_Checker{ pc: usize, sp: usize, sections: Vec
, @@ -91,7 +91,7 @@ struct Mem_Checker{ impl Mem_Checker{ - fn from(path: &String) -> Mem_Checker { + pub fn from(path: &String) -> Mem_Checker { let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); let reader = io::BufReader::new(file); @@ -151,7 +151,7 @@ impl Mem_Checker{ } - fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ + pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ machine.sp = m_c.sp; machine.pc = m_c.pc as u64; From 6507b601e7e2d94ffea055e90ec2292cd1fc11c0 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 15 Feb 2023 17:20:10 +0100 Subject: [PATCH 089/128] Added loader --- src/simulator/loader.rs | 33 +++++++++++++++++++++++++++++++++ src/simulator/mod.rs | 2 +- 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 src/simulator/loader.rs diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs new file mode 100644 index 0000000..0391aed --- /dev/null +++ b/src/simulator/loader.rs @@ -0,0 +1,33 @@ +use crate::Machine; + +use std::fs; +use std::io; +use std::io::BufRead; + + + + /// Load a file into a new machine + /// + /// `panic!` when size is not 1, 2, 4 or 8 + /// `panic!` when the text does not represents instructions in hexadecimal + /// + /// ### Parameters + /// + /// - **path** the path of the file to load + /// - **size** the number of bytes to write (1, 2, 4 or 8) +pub fn load(path : &str, instruction_size: i32) -> Machine { + let file = fs::File::open(path).expect("Wrong filename"); + let reader = io::BufReader::new(file); + let mut machine = Machine::_init_machine(); + + for (i,line) in reader.lines().enumerate() { + let res = u64::from_str_radix(&line.unwrap(), 16); + match res { + Ok(value) => { + Machine::write_memory(&mut machine, instruction_size, i, value); + }, + _ => panic!() + } + } + machine +} \ No newline at end of file diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 54d271e..6ee59e2 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -2,7 +2,7 @@ pub mod machine; pub mod decode; pub mod print; pub mod mem_cmp; - +pub mod loader; pub mod global { From 39b7db864a64671119d62d9fdefbe607b82461af Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 15 Feb 2023 18:01:50 +0100 Subject: [PATCH 090/128] calling mem_checker in main --- src/main.rs | 13 +++--- src/simulator/machine.rs | 5 ++- src/simulator/mem_cmp.rs | 91 +++++++++++++++++++++------------------- test_file_section.txt | 32 +++++++------- 4 files changed, 75 insertions(+), 66 deletions(-) diff --git a/src/main.rs b/src/main.rs index 4acaaf7..41ec194 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,14 +1,13 @@ mod simulator; use simulator::machine::Machine; +use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); - m.main_memory[4] = 43; - m.main_memory[5] = 150; - let a : u8 = 128; - let b : i8 = a as i8; - let c : u8 = b as u8; - println!("aaa {c}"); - println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4)); + let path = "test_file_section.txt".to_string(); + let checker = mem_cmp::Mem_Checker::from(&path); + mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); + Machine::run(m); + mem_cmp::Mem_Checker::print_Mem_Checker(&checker); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index f3f635b..4b80ffd 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -155,7 +155,7 @@ impl Machine { /// - **machine** which contains a table of instructions pub fn run(machine : Machine){ let mut m = machine; - loop{ + for i in 0..MEM_SIZE{ Machine::one_instruction(&mut m); } } @@ -190,7 +190,8 @@ impl Machine { let val = u64::from_le_bytes(val); let inst : Instruction = decode(val); - + print!("executing instruction {}\n", val); + print!("executing instruction {}\n", inst.opcode); match inst.opcode { RISCV_LUI => { diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index c4a8a5a..8b3bed4 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -1,6 +1,8 @@ use std::fs; use std::io; use std::io::BufRead; +use std::io::BufReader; +use std::io::Lines; use crate::Machine; const MEM_SIZE : usize = 4096; @@ -30,14 +32,14 @@ const MEM_SIZE : usize = 4096; //content est une suite hexadécimale //Section dans le fichier, champ String car informations proviennent d'un fichier txt -struct SectionFormat{ +pub struct SectionFormat{ addr: String, len: String, content: String, } //Section dans le programme -struct Section{ +pub struct Section{ addr: usize, // adresse dans la mémoire len: usize, // nombre d'octets de la donnée à addr content: Vec, // la donnée en question @@ -82,7 +84,7 @@ impl Section{ /* * Representation de l'etat de la mémoire (apres execution.... a confirmer), sous forme de sections */ -struct Mem_Checker{ +pub struct Mem_Checker{ pc: usize, sp: usize, sections: Vec
, @@ -91,59 +93,60 @@ struct Mem_Checker{ impl Mem_Checker{ - fn from(path: &String) -> Mem_Checker { + fn vect_from_lines(lines: &mut Lines>, pc: &mut usize, sp: &mut usize) -> Vec{ + let mut vector = Vec::new(); + for (i,line) in lines.enumerate() { + vector.push(line.unwrap()); + } + let size = vector.len(); + *pc = string_hex_to_usize(vector.get(size - 2).expect("0")); + *sp = string_hex_to_usize(vector.get(size - 1).expect("0")); + vector + } + + pub fn from(path: &String) -> Mem_Checker { let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); - let reader = io::BufReader::new(&file); - let reader2 = io::BufReader::new(&file); - let lines = reader.lines(); - let length = reader2.lines().count(); - + + let reader = io::BufReader::new(file); + let mut lines = reader.lines(); + let mut pc: usize = 0; let mut sp: usize = 0; + let vector = Mem_Checker::vect_from_lines(&mut lines, &mut pc, &mut sp); + let mut sections: Vec
= Vec::new(); - let mut tmp_addr_str: String = String::new(); let mut tmp_len_str: String = String::new(); + + let default = String::new(); + for i in 0..vector.len()-2 { + let current_line = vector.get(i).unwrap_or(&default); - for (i,line) in lines.enumerate() { - - let current_line = line.unwrap(); - - if i == length-2 { - //Lecture de PC - pc = string_hex_to_usize(¤t_line); - } - else if i == length-1 { - //Lecture SP - sp = string_hex_to_usize(¤t_line); + //Lecture des sections + if current_line.contains(' ') { + //lecture ligne ADDR LEN + let next_word_index = current_line.find(' ').unwrap(); + tmp_addr_str = String::from(¤t_line[0..next_word_index]); + tmp_len_str = String::from(¤t_line[next_word_index+1..]); } else { - //Lecture des sections - if current_line.contains(' ') { - //lecture ligne ADDR LEN - let next_word_index = current_line.find(' ').unwrap(); - tmp_addr_str = String::from(¤t_line[0..next_word_index]); - tmp_len_str = String::from(¤t_line[next_word_index+1..]); - } - else { - //lecture ligne CONTENT - let section_f = SectionFormat{ - addr: tmp_addr_str.clone(), - len: tmp_len_str.clone(), - content: current_line, - }; - sections.push(Section::from(§ion_f)); - } - + //lecture ligne CONTENT + let section_f = SectionFormat{ + addr: tmp_addr_str.clone(), + len: tmp_len_str.clone(), + content: current_line.clone(), + }; + sections.push(Section::from(§ion_f)); } - } + } + Mem_Checker{pc:pc, sp:sp, sections:sections} } - fn print_Mem_Checker(m_c: &Mem_Checker){ + pub fn print_Mem_Checker(m_c: &Mem_Checker){ println!("PC :: {}", m_c.pc); println!("SP :: {}", m_c.sp); @@ -154,7 +157,7 @@ impl Mem_Checker{ } - fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ + pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ machine.sp = m_c.sp; machine.pc = m_c.pc as u64; @@ -195,7 +198,11 @@ impl Mem_Checker{ -fn string_hex_to_usize(s: &String) -> usize{ +fn string_hex_to_usize(s: &String) -> usize { + + if s.len() == 0 { + return 0; + } let max_pow = (s.len()-1) as u32; let mut ret_value: usize = 0; diff --git a/test_file_section.txt b/test_file_section.txt index df1b0d2..21571c8 100644 --- a/test_file_section.txt +++ b/test_file_section.txt @@ -1,15 +1,17 @@ -addi sp,sp,-32 -sd s0,24(sp) -addi s0,sp,32 -sw zero,-20(s0) -li a5,1 -sw a5,-24(s0) -lw a5,-20(s0) -mv a4,a5 -lw a5,-24(s0) -addw a5,a4,a5 -sw a5,-20(s0) -nop -ld s0,24(sp) -addi sp,sp,32 -ret \ No newline at end of file +fe010113 +00813c23 +02010413 +fe042623 +00100793 +fef42423 +fec42783 +00078713 +fe842783 +00f707bb +fef42623 +00000013 +01813403 +02010113 +00008067 +0 +0 \ No newline at end of file From 82c9282f0ee41a79ab744e762a3b8f583775b2a5 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Wed, 15 Feb 2023 18:09:18 +0100 Subject: [PATCH 091/128] debug loader --- src/main.rs | 13 +++++-- src/simulator/loader.rs | 1 + src/simulator/machine.rs | 34 +++++++++++-------- .../simple_arithmerics/unsigned_addition.hex | 15 ++++++++ 4 files changed, 46 insertions(+), 17 deletions(-) create mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex diff --git a/src/main.rs b/src/main.rs index 4acaaf7..46ca3ff 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,14 +1,21 @@ mod simulator; use simulator::machine::Machine; +use simulator::loader; fn main() { - let mut m = Machine::_init_machine(); + + let mut m = loader::load("test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex", 4); + + Machine::run(m); + + /*let mut m = Machine::_init_machine(); m.main_memory[4] = 43; m.main_memory[5] = 150; let a : u8 = 128; let b : i8 = a as i8; let c : u8 = b as u8; println!("aaa {c}"); - println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4)); -} + println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4));*/ + +} \ No newline at end of file diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs index 0391aed..5659003 100644 --- a/src/simulator/loader.rs +++ b/src/simulator/loader.rs @@ -29,5 +29,6 @@ pub fn load(path : &str, instruction_size: i32) -> Machine { _ => panic!() } } + println!("{:x}", Machine::read_memory(& mut machine, 4, 0)); machine } \ No newline at end of file diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index f3f635b..c088af5 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -183,13 +183,14 @@ impl Machine { println!("ERROR : number max of instructions rushed"); return ; } - let mut val: [u8; 8] = [0; 8]; - for i in 0..8 { + let mut val: [u8; 4] = [0; 4]; + for i in 0..4 { val[i] = machine.main_memory[machine.pc as usize + i]; } - let val = u64::from_le_bytes(val); - let inst : Instruction = decode(val); + let val = u32::from_be_bytes(val); + println!("{:x}", val); + let inst : Instruction = decode(val as u64); match inst.opcode { @@ -197,11 +198,11 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); }, RISCV_AUIPC => { - machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64); + machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); }, RISCV_JAL => { machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); - machine.pc += inst.imm21_1_signed as u64 - 8; + machine.pc += inst.imm21_1_signed as u64 - 4; }, RISCV_JALR => { let tmp = machine.pc; @@ -215,32 +216,32 @@ impl Machine { match inst.funct3 { RISCV_BR_BEQ => { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BNE => { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLT => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGE => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLTU => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGEU => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 8; + machine.pc += inst.imm13_signed as u64 - 4; } }, _ => { @@ -602,10 +603,10 @@ impl Machine { } } } - _ => { panic!("{} opcode non géré", inst.opcode)}, + _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, } - machine.pc += 8; + machine.pc += 4; // Possible bug avec jump } } @@ -628,5 +629,10 @@ impl Machine { Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); assert_eq!(43, m.main_memory[6]); assert_eq!(150, m.main_memory[7]); + Machine::write_memory(&mut m, 4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150); + assert_eq!(52, m.main_memory[8]); + assert_eq!(20, m.main_memory[9]); + assert_eq!(43, m.main_memory[10]); + assert_eq!(150, m.main_memory[11]); } } diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex new file mode 100644 index 0000000..d5a8502 --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex @@ -0,0 +1,15 @@ +fe010113 +00813c23 +02010413 +fe042623 +00100793 +fef42423 +fec42783 +00078713 +fe842783 +00f707bb +fef42623 +00000013 +01813403 +02010113 +00008067 \ No newline at end of file From b86331503051a9a1e5250ca767febb25c0868fe0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Thu, 16 Feb 2023 15:48:26 +0100 Subject: [PATCH 092/128] updated gitignore --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index ea8c4bf..d114b83 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,3 @@ /target +/.idea +*.iml \ No newline at end of file From afe643170f561669fdabe977032e541844ea4368 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 1 Mar 2023 13:44:48 +0100 Subject: [PATCH 093/128] Automated objdumping of test programs --- test_programs/.gitignore | 4 +++ test_programs/Makefile | 9 +++---- test_programs/Makefile.config | 5 ++-- test_programs/Makefile.dumps | 12 +++++++++ test_programs/Makefile.objdumps | 24 ------------------ test_programs/riscv_instructions/Makefile | 6 +++-- .../riscv_instructions/boolean_logic/Makefile | 4 +++ .../jump_instructions/Makefile | 4 +++ .../simple_arithmerics/unsigned_addition.hex | 15 ----------- .../simple_arithmerics/unsigned_addition.o | Bin 1088 -> 0 bytes .../simple_arithmetics/Makefile | 4 +++ .../README.md | 0 .../unsigned_addition.c | 0 .../unsigned_division.c | 0 .../unsigned_multiplication.c | 0 .../unsigned_substraction.c | 0 16 files changed, 39 insertions(+), 48 deletions(-) create mode 100644 test_programs/.gitignore create mode 100644 test_programs/Makefile.dumps delete mode 100644 test_programs/Makefile.objdumps create mode 100644 test_programs/riscv_instructions/boolean_logic/Makefile create mode 100644 test_programs/riscv_instructions/jump_instructions/Makefile delete mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex delete mode 100644 test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o create mode 100644 test_programs/riscv_instructions/simple_arithmetics/Makefile rename test_programs/riscv_instructions/{simple_arithmerics => simple_arithmetics}/README.md (100%) rename test_programs/riscv_instructions/{simple_arithmerics => simple_arithmetics}/unsigned_addition.c (100%) rename test_programs/riscv_instructions/{simple_arithmerics => simple_arithmetics}/unsigned_division.c (100%) rename test_programs/riscv_instructions/{simple_arithmerics => simple_arithmetics}/unsigned_multiplication.c (100%) rename test_programs/riscv_instructions/{simple_arithmerics => simple_arithmetics}/unsigned_substraction.c (100%) diff --git a/test_programs/.gitignore b/test_programs/.gitignore new file mode 100644 index 0000000..0a0178a --- /dev/null +++ b/test_programs/.gitignore @@ -0,0 +1,4 @@ +# Ignoring dump files +*.dump +*.o +./target \ No newline at end of file diff --git a/test_programs/Makefile b/test_programs/Makefile index e15867e..662a888 100644 --- a/test_programs/Makefile +++ b/test_programs/Makefile @@ -4,11 +4,10 @@ include $(TOPDIR)/Makefile.config # # Main targets # -objdumps: - $(MAKE) -C riscv_instructions - -programs: - $(MAKE) -C programs +dumps: + $(MAKE) dumps -C riscv_instructions/ + mkdir -p ${TOPDIR}/target + find . -name '*.dump' -exec mv {} ${TOPDIR}/target \; clean: rm -rf $(TOPDIR)/target \ No newline at end of file diff --git a/test_programs/Makefile.config b/test_programs/Makefile.config index fca5849..47436e8 100644 --- a/test_programs/Makefile.config +++ b/test_programs/Makefile.config @@ -11,8 +11,9 @@ RISCV_PREFIX=/opt/riscv/bin/ RISCV_AS = $(RISCV_PREFIX)riscv64-unknown-elf-gcc -x assembler-with-cpp -march=rv64imfd RISCV_GCC = $(RISCV_PREFIX)riscv64-unknown-elf-gcc RISCV_LD = $(RISCV_PREFIX)riscv64-unknown-elf-ld -RISCV_OBJDUMP = $(RISCV_PREFIX)riscv64-unknown-elf-objdump +RISCV_OBJCOPY = $(RISCV_PREFIX)riscv64-unknown-elf-objcopy +DUMP_FORMAT = ihex RISCV_ASFLAGS = $(RISCV_CPPFLAGS) RISCV_CPPFLAGS = #nil RISCV_CFLAGS = -Wall $(RISCV_CPPFLAGS) -march=rv64imfd -RISCV_LDFLAGS = #nil +RISCV_LDFLAGS = #nil \ No newline at end of file diff --git a/test_programs/Makefile.dumps b/test_programs/Makefile.dumps new file mode 100644 index 0000000..a9824c1 --- /dev/null +++ b/test_programs/Makefile.dumps @@ -0,0 +1,12 @@ +include $(TOPDIR)/Makefile.config + +%.o: %.c + $(RISCV_GCC) $(RISCV_CFLAGS) -c $< + + +%.dump: %.o + $(RISCV_OBJCOPY) -j .text -O $(DUMP_FORMAT) $< $@ + +clean: + rm -rf *.o 2> /dev/null + rm -rf *.dump 2> /dev/null \ No newline at end of file diff --git a/test_programs/Makefile.objdumps b/test_programs/Makefile.objdumps deleted file mode 100644 index 78a4520..0000000 --- a/test_programs/Makefile.objdumps +++ /dev/null @@ -1,24 +0,0 @@ -include $(TOPDIR)/Makefile.config - -COVERAGE = $(TOPDIR)/riscv_instructions - -AS = $(RISCV_AS) -c -GCC = $(RISCV_GCC) -LD = $(RISCV_LD) - -INCPATH += -I$(TOPDIR) -I$(COVERAGE) -ASFLAGS = $(RISCV_ASFLAGS) $(INCPATH) -CFLAGS = $(RISCV_CFLAGS) $(INCPATH) - -# Rules -%.a: - $(AR) rcv $@ $^ - -%.o: %.c - $(GCC) $(CFLAGS) -c $< - -%.o: %.s - $(AS) $(ASFLAGS) -c $< - -$(PROGRAMS): - $(LD) $+ -o $@ \ No newline at end of file diff --git a/test_programs/riscv_instructions/Makefile b/test_programs/riscv_instructions/Makefile index 29df4bd..c134d5f 100644 --- a/test_programs/riscv_instructions/Makefile +++ b/test_programs/riscv_instructions/Makefile @@ -1,2 +1,4 @@ -TOPDIR = ../ -include $(TOPDIR)/Makefile.objdumps +dumps: + make dumps -C boolean_logic/ + make dumps -C jump_instructions/ + make dumps -C simple_arithmetics/ \ No newline at end of file diff --git a/test_programs/riscv_instructions/boolean_logic/Makefile b/test_programs/riscv_instructions/boolean_logic/Makefile new file mode 100644 index 0000000..2150f14 --- /dev/null +++ b/test_programs/riscv_instructions/boolean_logic/Makefile @@ -0,0 +1,4 @@ +TOPDIR = ../.. +include $(TOPDIR)/Makefile.dumps + +dumps: comparisons.dump if.dump switch.dump \ No newline at end of file diff --git a/test_programs/riscv_instructions/jump_instructions/Makefile b/test_programs/riscv_instructions/jump_instructions/Makefile new file mode 100644 index 0000000..75b887b --- /dev/null +++ b/test_programs/riscv_instructions/jump_instructions/Makefile @@ -0,0 +1,4 @@ +TOPDIR = ../.. +include $(TOPDIR)/Makefile.dumps + +dumps: jump.dump ret.dump \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex deleted file mode 100644 index d5a8502..0000000 --- a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex +++ /dev/null @@ -1,15 +0,0 @@ -fe010113 -00813c23 -02010413 -fe042623 -00100793 -fef42423 -fec42783 -00078713 -fe842783 -00f707bb -fef42623 -00000013 -01813403 -02010113 -00008067 \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o deleted file mode 100644 index 3d69445f952a67be3ab705cbfff4767457813b8b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1088 zcmbtTPfG$(5TE^H>dlfOs6bJ)ARen}M0hZyy!0Jp)y4L(tGG`w2uck40A2hdow{`B zL-aKwq1)CxdoLd^>EgidZ{|1id-G=4y*g?AqtcHefS*xgiLN0CQ)aU#u{q$&K(BzTJ1Eo-zhpy z*(n`aR^j9zRVb1ovEVF)`Mw*phM;YsYbGN7;c>|=_N<17FQoo8HiHT8U(1S&F4UDh7Vwc6_JZu-k2yx?P{NAUgujc6|U6 zTzk}RBGUd3UI~vnBMPK#QyWM#2!OP@p6B?;&9_NxO8aheK%GEzS_yYh&9<szKHD3M2@Ol;0jpwl-wu1f;wd_pwgA)CBF(;eoFR+YByn9csVg8g8X(b_a zf@ZPwYY7@&xc9~}ipb_<4>R`NFpJ}(?vC+O-e`{nlBxaIF}FpF diff --git a/test_programs/riscv_instructions/simple_arithmetics/Makefile b/test_programs/riscv_instructions/simple_arithmetics/Makefile new file mode 100644 index 0000000..d775b97 --- /dev/null +++ b/test_programs/riscv_instructions/simple_arithmetics/Makefile @@ -0,0 +1,4 @@ +TOPDIR = ../.. +include $(TOPDIR)/Makefile.dumps + +dumps: unsigned_addition.dump unsigned_division.dump unsigned_multiplication.dump unsigned_substraction.dump \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmerics/README.md b/test_programs/riscv_instructions/simple_arithmetics/README.md similarity index 100% rename from test_programs/riscv_instructions/simple_arithmerics/README.md rename to test_programs/riscv_instructions/simple_arithmetics/README.md diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c similarity index 100% rename from test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.c rename to test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c similarity index 100% rename from test_programs/riscv_instructions/simple_arithmerics/unsigned_division.c rename to test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c similarity index 100% rename from test_programs/riscv_instructions/simple_arithmerics/unsigned_multiplication.c rename to test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c similarity index 100% rename from test_programs/riscv_instructions/simple_arithmerics/unsigned_substraction.c rename to test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c From 8c737f4c42ac0a7ca0689d77eddd3bfb9f5c29c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 1 Mar 2023 13:46:19 +0100 Subject: [PATCH 094/128] Updated README.md --- test_programs/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test_programs/README.md b/test_programs/README.md index 6e73dba..018ecb2 100644 --- a/test_programs/README.md +++ b/test_programs/README.md @@ -11,7 +11,7 @@ Set the variables to the correct paths for the [RISCV Newlib compilation toolcha ### Exporting objdumps ``` -$ make objdumps +$ make dumps ``` ### Compiling programs From f6ff30b63caa4ec17d6f1ec5729fd961a3bda6cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 1 Mar 2023 13:56:12 +0100 Subject: [PATCH 095/128] Fixed compilation warnings --- test_programs/riscv_instructions/boolean_logic/comparisons.c | 2 +- test_programs/riscv_instructions/boolean_logic/switch.c | 4 ++-- test_programs/riscv_instructions/jump_instructions/jump.c | 3 ++- .../riscv_instructions/simple_arithmetics/unsigned_addition.c | 2 +- .../riscv_instructions/simple_arithmetics/unsigned_division.c | 2 +- .../simple_arithmetics/unsigned_multiplication.c | 2 +- .../simple_arithmetics/unsigned_substraction.c | 2 +- 7 files changed, 9 insertions(+), 8 deletions(-) diff --git a/test_programs/riscv_instructions/boolean_logic/comparisons.c b/test_programs/riscv_instructions/boolean_logic/comparisons.c index f653fff..ec42461 100644 --- a/test_programs/riscv_instructions/boolean_logic/comparisons.c +++ b/test_programs/riscv_instructions/boolean_logic/comparisons.c @@ -9,7 +9,7 @@ int main() { } else if (x < y) { y += 1; } else { - return; + return 0; } } } \ No newline at end of file diff --git a/test_programs/riscv_instructions/boolean_logic/switch.c b/test_programs/riscv_instructions/boolean_logic/switch.c index 86a181c..4ad23b2 100644 --- a/test_programs/riscv_instructions/boolean_logic/switch.c +++ b/test_programs/riscv_instructions/boolean_logic/switch.c @@ -1,7 +1,7 @@ int main() { int x = 0; - switch(1) { + switch(x) { case 1: x = 1; break; - default: return; + default: return 0; } } \ No newline at end of file diff --git a/test_programs/riscv_instructions/jump_instructions/jump.c b/test_programs/riscv_instructions/jump_instructions/jump.c index c4fd641..99f98b8 100644 --- a/test_programs/riscv_instructions/jump_instructions/jump.c +++ b/test_programs/riscv_instructions/jump_instructions/jump.c @@ -1,7 +1,8 @@ int test() { - return 1; + return 0; } int main() { int x = test(); + return x; } \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c index 2881ac7..05a7829 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c +++ b/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c @@ -1,5 +1,5 @@ // EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 1 -void main() { +int main() { unsigned int x = 0; unsigned int y = 1; x = x + y; diff --git a/test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c index 729f889..8e71c25 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c +++ b/test_programs/riscv_instructions/simple_arithmetics/unsigned_division.c @@ -1,5 +1,5 @@ // Expecting two variables with a value of two -void main() { +int main() { unsigned int x = 4; unsigned int y = 2; x = x / y; diff --git a/test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c index c79294d..f83e4f0 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c +++ b/test_programs/riscv_instructions/simple_arithmetics/unsigned_multiplication.c @@ -1,5 +1,5 @@ // EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 2 -void main() { +int main() { unsigned int x = 1; unsigned int y = 2; x = x * y; diff --git a/test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c index dd4e09b..e2b7ec4 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c +++ b/test_programs/riscv_instructions/simple_arithmetics/unsigned_substraction.c @@ -1,5 +1,5 @@ // EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 1 -void main() { +int main() { unsigned int x = 1; unsigned int y = 1; x = x - y; From 73c49414ff120b549005d607fa444268d483728b Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Mar 2023 15:11:35 +0100 Subject: [PATCH 096/128] print_memory dans Machine --- src/main.rs | 8 +++----- src/simulator/loader.rs | 2 +- src/simulator/machine.rs | 11 +++++++++++ src/simulator/mem_cmp.rs | 6 +++--- src/simulator/print.rs | 2 +- 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/main.rs b/src/main.rs index 41ec194..b245e37 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,13 +1,11 @@ mod simulator; use simulator::machine::Machine; -use simulator::mem_cmp; +use simulator::{mem_cmp, loader}; fn main() { - let mut m = Machine::_init_machine(); let path = "test_file_section.txt".to_string(); - let checker = mem_cmp::Mem_Checker::from(&path); - mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); + let mut m = loader::load(&path, 4); + Machine::print_memory(&mut m); Machine::run(m); - mem_cmp::Mem_Checker::print_Mem_Checker(&checker); } diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs index 5659003..7d31d18 100644 --- a/src/simulator/loader.rs +++ b/src/simulator/loader.rs @@ -24,7 +24,7 @@ pub fn load(path : &str, instruction_size: i32) -> Machine { let res = u64::from_str_radix(&line.unwrap(), 16); match res { Ok(value) => { - Machine::write_memory(&mut machine, instruction_size, i, value); + Machine::write_memory(&mut machine, instruction_size, i*instruction_size as usize, value); }, _ => panic!() } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 662ae2d..e7af292 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -609,6 +609,17 @@ impl Machine { machine.pc += 4; // Possible bug avec jump } + + pub fn print_memory(machine : &mut Machine) { + for i in 0..MEM_SIZE { + if i%16 == 0 { + print!("\n@{:04x} ", i); + } + print!("{:02x}", machine.main_memory[i]); + } + println!(); + } + } #[cfg(test)] diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 8b3bed4..5c81029 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -232,11 +232,11 @@ fn one_hex_to_dec(c: char) -> u8 { 'E' | 'e' => 14, 'F' | 'f' => 15, _ => { - let ret : u8 = c.to_digit(10).unwrap() as u8; + let ret : u8 = c.to_digit(10).unwrap() as u8; return ret; - }, - } + }, } +} diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 4cf103b..0539a43 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -217,7 +217,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_SYSTEM => { "ecall".to_string() }, - _ => todo!("Unknown or currently unsupported opcode") // Change todo! to panic! in the future, I put todo! because there's a lot of opcode currently not implemented + _ => todo!("{:x} opcode non géré pc : {:x}, value : {:x}", ins.opcode, pc, ins.value) // Change todo! to panic! in the future, I put todo! because there's a lot of opcode currently not implemented } } From e82af4ae67eb1ed46b7517f6f9f8849d7356f2f5 Mon Sep 17 00:00:00 2001 From: amaury Date: Wed, 1 Mar 2023 15:21:18 +0100 Subject: [PATCH 097/128] ajout du fichier memoire --- memory.txt | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 memory.txt diff --git a/memory.txt b/memory.txt new file mode 100644 index 0000000..41a6de2 --- /dev/null +++ b/memory.txt @@ -0,0 +1,8 @@ +4000 1b8 +ffffff97 ffffffd0 3f 0 ffffffe7 ffffff80 0 41 13 5 0 0 ffffffef 0 40 1 67 ffffff80 0 0 ffffff93 8 0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 10 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 20 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 30 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 40 0 73 0 0 0 67 ffffff80 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3 37 ffffff84 fffffff5 33 7 fffffff7 0 ffffff83 37 ffffff84 fffffff6 ffffff93 ffffff86 17 0 23 34 ffffffd4 fffffff6 3 47 7 0 23 ffffff80 ffffffe7 0 ffffff83 27 ffffff84 fffffffe ffffff9b ffffff87 17 0 23 24 fffffff4 fffffffe ffffff83 27 ffffffc4 fffffffe ffffff9b ffffff87 17 0 23 26 fffffff4 fffffffe ffffff83 27 ffffffc4 fffffffe 3 37 ffffff84 fffffff5 ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 63 ffffff94 7 ffffffea ffffff83 37 ffffff84 fffffff6 23 ffffff80 7 0 ffffff83 27 ffffff84 fffffffe 13 ffffff85 7 0 3 34 ffffff81 a 13 1 1 b 67 ffffff80 0 0 13 1 1 fffffff9 23 3c 11 2 23 38 ffffff81 2 13 4 1 4 23 3c ffffffa4 fffffffc 23 34 ffffffc4 fffffffc 23 34 ffffffd4 0 23 38 ffffffe4 0 23 3c fffffff4 0 23 30 4 3 23 34 14 3 ffffff93 ffffff87 5 0 23 2a fffffff4 fffffffc ffffff93 7 4 3 23 30 fffffff4 fffffffc ffffff83 37 4 fffffffc ffffff93 ffffff87 ffffff87 fffffffd 23 34 fffffff4 fffffffe 3 37 ffffff84 fffffffe ffffff83 27 44 fffffffd ffffff93 6 7 0 3 36 ffffff84 fffffffc ffffff93 ffffff85 7 0 3 35 ffffff84 fffffffd ffffffef fffffff0 ffffff8f ffffffdd ffffff93 7 5 0 23 2a fffffff4 fffffffc ffffff83 27 44 fffffffd 13 ffffff85 7 0 ffffff83 30 ffffff81 3 3 34 1 3 13 1 1 7 67 ffffff80 0 0 13 1 1 ffffffec 23 3c 11 e 23 38 ffffff81 e 13 4 1 10 23 34 ffffffa4 fffffff0 23 34 ffffffb4 0 23 38 ffffffc4 0 23 3c ffffffd4 0 23 30 ffffffe4 2 23 34 fffffff4 2 23 38 4 3 23 3c 14 3 ffffff93 7 4 4 23 30 fffffff4 fffffff0 ffffff83 37 4 fffffff0 ffffff93 ffffff87 ffffff87 fffffffc 23 30 fffffff4 fffffffe 3 37 4 fffffffe ffffff93 7 ffffff84 fffffff1 ffffff93 6 7 0 3 36 ffffff84 fffffff0 ffffff93 5 ffffff80 c 13 ffffff85 7 0 ffffffef fffffff0 ffffff8f ffffffd5 ffffff93 7 5 0 23 26 fffffff4 fffffffe ffffff83 27 ffffffc4 fffffffe 13 ffffff87 7 0 ffffff93 7 70 c 63 fffffff6 ffffffe7 0 ffffff93 7 70 c 23 26 fffffff4 fffffffe ffffff83 27 ffffffc4 fffffffe ffffff9b ffffff87 7 0 63 50 fffffff0 2 3 27 ffffffc4 fffffffe ffffff93 7 ffffff84 fffffff1 13 6 10 0 ffffff93 5 7 0 13 ffffff85 7 0 ffffff97 30 ffffffc0 ffffffff ffffffe7 ffffff80 0 ffffffcc 13 0 0 0 ffffff83 30 ffffff81 f 3 34 1 f 13 1 1 14 67 ffffff80 0 0 13 1 1 fffffff2 23 3c 11 c 23 38 ffffff81 c 13 4 1 e ffffff93 7 ffffff84 fffffff2 13 6 0 0 ffffff93 5 ffffff80 c 13 ffffff85 7 0 ffffff97 30 ffffffc0 ffffffff ffffffe7 ffffff80 ffffff80 ffffffc7 ffffff93 7 ffffff84 fffffff2 13 ffffff85 7 0 ffffffef ffffffe0 ffffff9f ffffffff ffffff93 7 5 0 13 ffffff85 7 0 ffffff83 30 ffffff81 d 3 34 1 d 13 1 1 e 67 ffffff80 0 0 13 1 1 ffffffff 23 34 11 0 23 30 ffffff81 0 13 4 1 1 ffffffb7 47 40 0 13 ffffff85 7 8 ffffffef fffffff0 1f ffffffee ffffff93 7 0 0 13 ffffff85 7 0 ffffff83 30 ffffff81 0 3 34 1 0 13 1 1 1 67 ffffff80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +404000 a4 +25 78 9 0 0 0 0 0 20 20 20 0 0 0 0 0 25 73 20 0 0 0 0 0 a 0 0 0 0 0 0 0 28 6e 75 6c 6c 29 0 0 fffffff8 e 40 0 ffffffe8 9 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 ffffffe8 9 40 0 7c 11 40 0 7c 11 40 0 28 b 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 4c f 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 ffffffd0 f 40 0 2a 2a 20 2a 2a 20 2a 2a 20 42 6f 6e 6a 6f 75 72 20 6c 65 20 6d 6f 6e 64 65 20 2a 2a 20 2a 2a 20 2a 2a a 0 41 2a 0 0 0 72 69 73 63 76 0 1 20 0 0 0 4 10 5 72 76 36 34 69 32 70 30 5f 6d 32 70 30 5f 66 32 70 30 5f 64 32 70 30 0 47 43 43 3a 20 28 29 20 31 32 2e 32 2e 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 0 +4000 +4052f0 \ No newline at end of file From 5a90419ebb788da1f07d66af21afeff6cebca647 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Mar 2023 16:12:46 +0100 Subject: [PATCH 098/128] change memory to a vector, it can now be fill --- src/main.rs | 11 +++++++---- src/simulator/machine.rs | 24 +++++++++++++----------- src/simulator/mem_cmp.rs | 10 +++++----- test_file_section.txt | 19 ++----------------- 4 files changed, 27 insertions(+), 37 deletions(-) diff --git a/src/main.rs b/src/main.rs index b245e37..6e4d2c7 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,11 +1,14 @@ mod simulator; use simulator::machine::Machine; -use simulator::{mem_cmp, loader}; +use simulator::mem_cmp; fn main() { - let path = "test_file_section.txt".to_string(); - let mut m = loader::load(&path, 4); - Machine::print_memory(&mut m); + let mut m = Machine::_init_machine(); + let path = "memory.txt".to_string(); + let checker = mem_cmp::Mem_Checker::from(&path); + mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); + mem_cmp::Mem_Checker::print_Mem_Checker(&checker); + Machine::print_memory(&mut m, 0x400000, 0x405000); Machine::run(m); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e7af292..bd5617a 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -5,7 +5,7 @@ use super::global::*; use std::fs::File; /// doit disparaitre -const MEM_SIZE : usize = 4096; +const MEM_SIZE : usize = 0x500000; pub trait RegisterNum: Add + Sub + PartialEq + Copy {} @@ -65,7 +65,7 @@ pub struct Machine { pub sp: usize, pub int_reg : Register, pub fp_reg : Register, - pub main_memory : [u8 ; MEM_SIZE], + pub main_memory : Vec, pub shiftmask : [u64 ; 64] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg @@ -89,7 +89,7 @@ impl Machine { sp: 0, int_reg : Register::::init(), fp_reg : Register::::init(), - main_memory : [0 ; MEM_SIZE], + main_memory : vec![0; MEM_SIZE], shiftmask } @@ -180,17 +180,16 @@ impl Machine { uint64_t value;*/ if machine.main_memory.len() <= machine.pc as usize { - println!("ERROR : number max of instructions rushed"); - return ; + panic!("ERROR : number max of instructions rushed"); } - let mut val: [u8; 4] = [0; 4]; - for i in 0..4 { + let mut val: [u8; 8] = [0; 8]; + for i in 0..8 { val[i] = machine.main_memory[machine.pc as usize + i]; } - let val = u32::from_be_bytes(val); + let val = u64::from_be_bytes(val); println!("{:x}", val); - let inst : Instruction = decode(val as u64); + let inst : Instruction = decode(val); match inst.opcode { @@ -610,8 +609,11 @@ impl Machine { } - pub fn print_memory(machine : &mut Machine) { - for i in 0..MEM_SIZE { + /// print memory FOR DEBUG + /// + /// "@"adresse [16 bytes] + pub fn print_memory(machine : &mut Machine, from: usize, to: usize) { + for i in from..to { if i%16 == 0 { print!("\n@{:04x} ", i); } diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 5c81029..e90fec7 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -106,7 +106,7 @@ impl Mem_Checker{ pub fn from(path: &String) -> Mem_Checker { - let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); + let file = fs::File::open(path).expect("Wrong filename"); let reader = io::BufReader::new(file); let mut lines = reader.lines(); @@ -124,7 +124,7 @@ impl Mem_Checker{ let current_line = vector.get(i).unwrap_or(&default); //Lecture des sections - if current_line.contains(' ') { + if i % 2 == 0 { //lecture ligne ADDR LEN let next_word_index = current_line.find(' ').unwrap(); tmp_addr_str = String::from(¤t_line[0..next_word_index]); @@ -135,7 +135,7 @@ impl Mem_Checker{ let section_f = SectionFormat{ addr: tmp_addr_str.clone(), len: tmp_len_str.clone(), - content: current_line.clone(), + content: current_line.clone().replace(" ", ""), }; sections.push(Section::from(§ion_f)); } @@ -147,8 +147,8 @@ impl Mem_Checker{ pub fn print_Mem_Checker(m_c: &Mem_Checker){ - println!("PC :: {}", m_c.pc); - println!("SP :: {}", m_c.sp); + println!("PC :: {:x}", m_c.pc); + println!("SP :: {:x}", m_c.sp); for(i,s) in m_c.sections.iter().enumerate() { println!("\nSection {}\n", i); diff --git a/test_file_section.txt b/test_file_section.txt index 21571c8..81b6acd 100644 --- a/test_file_section.txt +++ b/test_file_section.txt @@ -1,17 +1,2 @@ -fe010113 -00813c23 -02010413 -fe042623 -00100793 -fef42423 -fec42783 -00078713 -fe842783 -00f707bb -fef42623 -00000013 -01813403 -02010113 -00008067 -0 -0 \ No newline at end of file +130101FE233C8100 +13040102232604FE From 45f9d9c0e091e347d83f16b5d1b40c72ea401543 Mon Sep 17 00:00:00 2001 From: amaury Date: Wed, 1 Mar 2023 16:26:55 +0100 Subject: [PATCH 099/128] nouveau memory.txt avec unsigned_addition --- memory.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/memory.txt b/memory.txt index 41a6de2..0a6fca8 100644 --- a/memory.txt +++ b/memory.txt @@ -1,8 +1,8 @@ 4000 1b8 ffffff97 ffffffd0 3f 0 ffffffe7 ffffff80 0 41 13 5 0 0 ffffffef 0 40 1 67 ffffff80 0 0 ffffff93 8 0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 10 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 20 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 30 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 40 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 50 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 60 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 70 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffff80 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffff90 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 fffffff0 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffa0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffe0 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffb0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffc0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffd0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffe0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 fffffff0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 0 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 0 2 73 0 0 0 67 ffffff80 0 0 ffffff93 8 10 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 20 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 30 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 40 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 50 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 60 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 70 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffff80 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffff90 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffa0 1 73 0 0 0 67 ffffff80 0 0 ffffff93 8 ffffffb0 1 73 0 0 0 67 ffffff80 0 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30 ffffff81 1 3 34 1 1 13 1 1 2 67 ffffff80 0 0 13 1 1 fffffffd 23 34 ffffff81 2 13 4 1 3 23 3c ffffffa4 fffffffc 23 38 ffffffb4 fffffffc 23 24 4 fffffffe 23 22 4 fffffffe 6f 0 40 b ffffff83 27 44 fffffffe 3 37 ffffff84 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 63 ffffff92 7 2 ffffff83 27 44 fffffffe 3 37 4 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 63 ffffff98 7 0 ffffff93 7 10 0 23 24 fffffff4 fffffffe 23 26 4 fffffffe ffffff83 27 44 fffffffe 3 37 ffffff84 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc6 7 0 ffffff83 27 44 fffffffe 3 37 4 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 13 ffffff87 6 0 63 7a fffffff7 0 ffffff93 7 10 0 23 24 fffffff4 fffffffe ffffff93 7 fffffff0 ffffffff 23 26 fffffff4 fffffffe ffffff83 27 44 fffffffe 3 37 ffffff84 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc6 7 0 ffffff83 27 44 fffffffe 3 37 4 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 13 ffffff87 6 0 63 fffffffa ffffffe7 0 ffffff93 7 10 0 23 24 fffffff4 fffffffe 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37 ffffff84 fffffffd 6f 0 ffffff80 0 ffffff93 7 0 0 13 ffffff85 7 0 3 34 ffffff81 2 13 1 1 3 67 ffffff80 0 0 13 1 1 fffffffd 23 34 ffffff81 2 13 4 1 3 23 3c ffffffa4 fffffffc 23 26 4 fffffffe 6f 0 0 1 ffffff83 27 ffffffc4 fffffffe ffffff9b ffffff87 17 0 23 26 fffffff4 fffffffe ffffff83 67 ffffffc4 fffffffe 3 37 ffffff84 fffffffd ffffffb3 7 fffffff7 0 ffffff83 ffffffc7 7 0 ffffffe3 ffffff92 7 fffffffe ffffff83 27 ffffffc4 fffffffe 13 ffffff85 7 0 3 34 ffffff81 2 13 1 1 3 67 ffffff80 0 0 13 1 1 fffffffd 23 34 11 2 23 30 ffffff81 2 13 4 1 3 23 3c ffffffa4 fffffffc 23 38 ffffffb4 fffffffc 3 35 ffffff84 fffffffd ffffffef fffffff0 ffffff9f fffffff9 ffffff93 7 5 0 ffffff9b ffffff87 7 0 23 24 fffffff4 fffffffe 3 35 4 fffffffd ffffffef fffffff0 5f fffffff8 ffffff93 7 5 0 ffffff9b ffffff87 7 0 23 22 fffffff4 fffffffe ffffff83 27 ffffff84 fffffffe 23 26 fffffff4 fffffffe 6f 0 40 4 ffffff83 27 ffffffc4 fffffffe 13 ffffff87 7 0 ffffff83 27 ffffff84 fffffffe ffffffbb 7 fffffff7 40 ffffff9b ffffff87 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0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 4c f 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 7c 11 40 0 ffffffd0 f 40 0 4000 -4052f0 \ No newline at end of file +S405270 \ No newline at end of file From d34b5b0067e20bd45355bee0bd3dc15fd54c2ecf Mon Sep 17 00:00:00 2001 From: amaury Date: Wed, 1 Mar 2023 17:19:18 +0100 Subject: [PATCH 100/128] memory.txt en hexa complet --- memory.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/memory.txt b/memory.txt index 0a6fca8..905bcdb 100644 --- a/memory.txt +++ b/memory.txt @@ -1,8 +1,8 @@ 4000 1b8 -ffffff97 ffffffd0 3f 0 ffffffe7 ffffff80 0 41 13 5 0 0 ffffffef 0 40 1 67 ffffff80 0 0 ffffff93 8 0 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 10 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 20 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 30 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 40 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 50 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 60 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 70 0 73 0 0 0 67 ffffff80 0 0 ffffff93 8 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+00000025 00000078 00000009 00000000 00000000 00000000 00000000 00000000 00000020 00000020 00000020 00000000 00000000 00000000 00000000 00000000 00000025 00000073 00000020 00000000 00000000 00000000 00000000 00000000 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000028 0000006e 00000075 0000006c 0000006c 00000029 00000000 00000000 fffffff8 0000000e 00000040 00000000 ffffffe8 00000009 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 ffffffe8 00000009 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 00000028 0000000b 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000004c 0000000f 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 ffffffd0 0000000f 00000040 00000000 +P4000 S405270 \ No newline at end of file From e61a92b490092d90d953acade3ca0064b8108e07 Mon Sep 17 00:00:00 2001 From: amaury Date: Wed, 1 Mar 2023 17:22:20 +0100 Subject: [PATCH 101/128] retrait des id de SP et PC et echange de @ et size --- file.txt | 483 ++++++++++++++++++++++++++++++++++++++++++++++++ memory.txt | 10 +- old_section.txt | 17 ++ 3 files changed, 505 insertions(+), 5 deletions(-) create mode 100644 file.txt create mode 100644 old_section.txt diff --git a/file.txt b/file.txt new file mode 100644 index 0000000..5caa50c --- /dev/null +++ b/file.txt @@ -0,0 +1,483 @@ + +./test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.o: file format elf64-littleriscv + + +Disassembly of section .text: + +00000000000100e8 : + 100e8: ff010113 addi sp,sp,-16 + 100ec: 00000593 li a1,0 + 100f0: 00813023 sd s0,0(sp) + 100f4: 00113423 sd ra,8(sp) + 100f8: 00050413 mv s0,a0 + 100fc: 29c000ef jal ra,10398 <__call_exitprocs> + 10100: f481b503 ld a0,-184(gp) # 11d78 <_global_impure_ptr> + 10104: 05853783 ld a5,88(a0) + 10108: 00078463 beqz a5,10110 + 1010c: 000780e7 jalr a5 + 10110: 00040513 mv a0,s0 + 10114: 4c4000ef jal ra,105d8 <_exit> + +0000000000010118 : + 10118: 00000793 li a5,0 + 1011c: 00078863 beqz a5,1012c + 10120: 00010537 lui a0,0x10 + 10124: 4c050513 addi a0,a0,1216 # 104c0 <__libc_fini_array> + 10128: 3f40006f j 1051c + 1012c: 00008067 ret + +0000000000010130 <_start>: + 10130: 00002197 auipc gp,0x2 + 10134: d0018193 addi gp,gp,-768 # 11e30 <__global_pointer$> + 10138: f6018513 addi a0,gp,-160 # 11d90 + 1013c: f9818613 addi a2,gp,-104 # 11dc8 <__BSS_END__> + 10140: 40a60633 sub a2,a2,a0 + 10144: 00000593 li a1,0 + 10148: 174000ef jal ra,102bc + 1014c: 00000517 auipc a0,0x0 + 10150: 3d050513 addi a0,a0,976 # 1051c + 10154: 00050863 beqz a0,10164 <_start+0x34> + 10158: 00000517 auipc a0,0x0 + 1015c: 36850513 addi a0,a0,872 # 104c0 <__libc_fini_array> + 10160: 3bc000ef jal ra,1051c + 10164: 0bc000ef jal ra,10220 <__libc_init_array> + 10168: 00012503 lw a0,0(sp) + 1016c: 00810593 addi a1,sp,8 + 10170: 00000613 li a2,0 + 10174: 06c000ef jal ra,101e0
+ 10178: f71ff06f j 100e8 + +000000000001017c <__do_global_dtors_aux>: + 1017c: ff010113 addi sp,sp,-16 + 10180: 00813023 sd s0,0(sp) + 10184: f601c783 lbu a5,-160(gp) # 11d90 + 10188: 00113423 sd ra,8(sp) + 1018c: 02079263 bnez a5,101b0 <__do_global_dtors_aux+0x34> + 10190: 00000793 li a5,0 + 10194: 00078a63 beqz a5,101a8 <__do_global_dtors_aux+0x2c> + 10198: 00011537 lui a0,0x11 + 1019c: 61050513 addi a0,a0,1552 # 11610 <__FRAME_END__> + 101a0: 00000097 auipc ra,0x0 + 101a4: 000000e7 jalr zero # 0 + 101a8: 00100793 li a5,1 + 101ac: f6f18023 sb a5,-160(gp) # 11d90 + 101b0: 00813083 ld ra,8(sp) + 101b4: 00013403 ld s0,0(sp) + 101b8: 01010113 addi sp,sp,16 + 101bc: 00008067 ret + +00000000000101c0 : + 101c0: 00000793 li a5,0 + 101c4: 00078c63 beqz a5,101dc + 101c8: 00011537 lui a0,0x11 + 101cc: f6818593 addi a1,gp,-152 # 11d98 + 101d0: 61050513 addi a0,a0,1552 # 11610 <__FRAME_END__> + 101d4: 00000317 auipc t1,0x0 + 101d8: 00000067 jr zero # 0 + 101dc: 00008067 ret + +00000000000101e0
: + 101e0: fe010113 addi sp,sp,-32 + 101e4: 00813c23 sd s0,24(sp) + 101e8: 02010413 addi s0,sp,32 + 101ec: fe042623 sw zero,-20(s0) + 101f0: 00100793 li a5,1 + 101f4: fef42423 sw a5,-24(s0) + 101f8: fec42783 lw a5,-20(s0) + 101fc: 00078713 mv a4,a5 + 10200: fe842783 lw a5,-24(s0) + 10204: 00f707bb addw a5,a4,a5 + 10208: fef42623 sw a5,-20(s0) + 1020c: 00000793 li a5,0 + 10210: 00078513 mv a0,a5 + 10214: 01813403 ld s0,24(sp) + 10218: 02010113 addi sp,sp,32 + 1021c: 00008067 ret + +0000000000010220 <__libc_init_array>: + 10220: fe010113 addi sp,sp,-32 + 10224: 00813823 sd s0,16(sp) + 10228: 000117b7 lui a5,0x11 + 1022c: 00011437 lui s0,0x11 + 10230: 01213023 sd s2,0(sp) + 10234: 61478793 addi a5,a5,1556 # 11614 <__preinit_array_end> + 10238: 61440713 addi a4,s0,1556 # 11614 <__preinit_array_end> + 1023c: 00113c23 sd ra,24(sp) + 10240: 00913423 sd s1,8(sp) + 10244: 40e78933 sub s2,a5,a4 + 10248: 02e78263 beq a5,a4,1026c <__libc_init_array+0x4c> + 1024c: 40395913 srai s2,s2,0x3 + 10250: 61440413 addi s0,s0,1556 + 10254: 00000493 li s1,0 + 10258: 00043783 ld a5,0(s0) + 1025c: 00148493 addi s1,s1,1 + 10260: 00840413 addi s0,s0,8 + 10264: 000780e7 jalr a5 + 10268: ff24e8e3 bltu s1,s2,10258 <__libc_init_array+0x38> + 1026c: 00011437 lui s0,0x11 + 10270: 000117b7 lui a5,0x11 + 10274: 62878793 addi a5,a5,1576 # 11628 <__do_global_dtors_aux_fini_array_entry> + 10278: 61840713 addi a4,s0,1560 # 11618 <__init_array_start> + 1027c: 40e78933 sub s2,a5,a4 + 10280: 40395913 srai s2,s2,0x3 + 10284: 02e78063 beq a5,a4,102a4 <__libc_init_array+0x84> + 10288: 61840413 addi s0,s0,1560 + 1028c: 00000493 li s1,0 + 10290: 00043783 ld a5,0(s0) + 10294: 00148493 addi s1,s1,1 + 10298: 00840413 addi s0,s0,8 + 1029c: 000780e7 jalr a5 + 102a0: ff24e8e3 bltu s1,s2,10290 <__libc_init_array+0x70> + 102a4: 01813083 ld ra,24(sp) + 102a8: 01013403 ld s0,16(sp) + 102ac: 00813483 ld s1,8(sp) + 102b0: 00013903 ld s2,0(sp) + 102b4: 02010113 addi sp,sp,32 + 102b8: 00008067 ret + +00000000000102bc : + 102bc: 00f00313 li t1,15 + 102c0: 00050713 mv a4,a0 + 102c4: 02c37a63 bgeu t1,a2,102f8 + 102c8: 00f77793 andi a5,a4,15 + 102cc: 0a079063 bnez a5,1036c + 102d0: 06059e63 bnez a1,1034c + 102d4: ff067693 andi a3,a2,-16 + 102d8: 00f67613 andi a2,a2,15 + 102dc: 00e686b3 add a3,a3,a4 + 102e0: 00b73023 sd a1,0(a4) + 102e4: 00b73423 sd a1,8(a4) + 102e8: 01070713 addi a4,a4,16 + 102ec: fed76ae3 bltu a4,a3,102e0 + 102f0: 00061463 bnez a2,102f8 + 102f4: 00008067 ret + 102f8: 40c306b3 sub a3,t1,a2 + 102fc: 00269693 slli a3,a3,0x2 + 10300: 00000297 auipc t0,0x0 + 10304: 005686b3 add a3,a3,t0 + 10308: 00c68067 jr 12(a3) + 1030c: 00b70723 sb a1,14(a4) + 10310: 00b706a3 sb a1,13(a4) + 10314: 00b70623 sb a1,12(a4) + 10318: 00b705a3 sb a1,11(a4) + 1031c: 00b70523 sb a1,10(a4) + 10320: 00b704a3 sb a1,9(a4) + 10324: 00b70423 sb a1,8(a4) + 10328: 00b703a3 sb a1,7(a4) + 1032c: 00b70323 sb a1,6(a4) + 10330: 00b702a3 sb a1,5(a4) + 10334: 00b70223 sb a1,4(a4) + 10338: 00b701a3 sb a1,3(a4) + 1033c: 00b70123 sb a1,2(a4) + 10340: 00b700a3 sb a1,1(a4) + 10344: 00b70023 sb a1,0(a4) + 10348: 00008067 ret + 1034c: 0ff5f593 zext.b a1,a1 + 10350: 00859693 slli a3,a1,0x8 + 10354: 00d5e5b3 or a1,a1,a3 + 10358: 01059693 slli a3,a1,0x10 + 1035c: 00d5e5b3 or a1,a1,a3 + 10360: 02059693 slli a3,a1,0x20 + 10364: 00d5e5b3 or a1,a1,a3 + 10368: f6dff06f j 102d4 + 1036c: 00279693 slli a3,a5,0x2 + 10370: 00000297 auipc t0,0x0 + 10374: 005686b3 add a3,a3,t0 + 10378: 00008293 mv t0,ra + 1037c: f98680e7 jalr -104(a3) + 10380: 00028093 mv ra,t0 + 10384: ff078793 addi a5,a5,-16 + 10388: 40f70733 sub a4,a4,a5 + 1038c: 00f60633 add a2,a2,a5 + 10390: f6c374e3 bgeu t1,a2,102f8 + 10394: f3dff06f j 102d0 + +0000000000010398 <__call_exitprocs>: + 10398: fb010113 addi sp,sp,-80 + 1039c: 03413023 sd s4,32(sp) + 103a0: f481ba03 ld s4,-184(gp) # 11d78 <_global_impure_ptr> + 103a4: 03213823 sd s2,48(sp) + 103a8: 04113423 sd ra,72(sp) + 103ac: 1f8a3903 ld s2,504(s4) + 103b0: 04813023 sd s0,64(sp) + 103b4: 02913c23 sd s1,56(sp) + 103b8: 03313423 sd s3,40(sp) + 103bc: 01513c23 sd s5,24(sp) + 103c0: 01613823 sd s6,16(sp) + 103c4: 01713423 sd s7,8(sp) + 103c8: 01813023 sd s8,0(sp) + 103cc: 04090063 beqz s2,1040c <__call_exitprocs+0x74> + 103d0: 00050b13 mv s6,a0 + 103d4: 00058b93 mv s7,a1 + 103d8: 00100a93 li s5,1 + 103dc: fff00993 li s3,-1 + 103e0: 00892483 lw s1,8(s2) + 103e4: fff4841b addiw s0,s1,-1 + 103e8: 02044263 bltz s0,1040c <__call_exitprocs+0x74> + 103ec: 00349493 slli s1,s1,0x3 + 103f0: 009904b3 add s1,s2,s1 + 103f4: 040b8463 beqz s7,1043c <__call_exitprocs+0xa4> + 103f8: 2084b783 ld a5,520(s1) + 103fc: 05778063 beq a5,s7,1043c <__call_exitprocs+0xa4> + 10400: fff4041b addiw s0,s0,-1 + 10404: ff848493 addi s1,s1,-8 + 10408: ff3416e3 bne s0,s3,103f4 <__call_exitprocs+0x5c> + 1040c: 04813083 ld ra,72(sp) + 10410: 04013403 ld s0,64(sp) + 10414: 03813483 ld s1,56(sp) + 10418: 03013903 ld s2,48(sp) + 1041c: 02813983 ld s3,40(sp) + 10420: 02013a03 ld s4,32(sp) + 10424: 01813a83 ld s5,24(sp) + 10428: 01013b03 ld s6,16(sp) + 1042c: 00813b83 ld s7,8(sp) + 10430: 00013c03 ld s8,0(sp) + 10434: 05010113 addi sp,sp,80 + 10438: 00008067 ret + 1043c: 00892783 lw a5,8(s2) + 10440: 0084b703 ld a4,8(s1) + 10444: fff7879b addiw a5,a5,-1 + 10448: 06878263 beq a5,s0,104ac <__call_exitprocs+0x114> + 1044c: 0004b423 sd zero,8(s1) + 10450: fa0708e3 beqz a4,10400 <__call_exitprocs+0x68> + 10454: 31092783 lw a5,784(s2) + 10458: 008a96bb sllw a3,s5,s0 + 1045c: 00892c03 lw s8,8(s2) + 10460: 00d7f7b3 and a5,a5,a3 + 10464: 0007879b sext.w a5,a5 + 10468: 02079263 bnez a5,1048c <__call_exitprocs+0xf4> + 1046c: 000700e7 jalr a4 + 10470: 00892703 lw a4,8(s2) + 10474: 1f8a3783 ld a5,504(s4) + 10478: 01871463 bne a4,s8,10480 <__call_exitprocs+0xe8> + 1047c: f92782e3 beq a5,s2,10400 <__call_exitprocs+0x68> + 10480: f80786e3 beqz a5,1040c <__call_exitprocs+0x74> + 10484: 00078913 mv s2,a5 + 10488: f59ff06f j 103e0 <__call_exitprocs+0x48> + 1048c: 31492783 lw a5,788(s2) + 10490: 1084b583 ld a1,264(s1) + 10494: 00d7f7b3 and a5,a5,a3 + 10498: 0007879b sext.w a5,a5 + 1049c: 00079c63 bnez a5,104b4 <__call_exitprocs+0x11c> + 104a0: 000b0513 mv a0,s6 + 104a4: 000700e7 jalr a4 + 104a8: fc9ff06f j 10470 <__call_exitprocs+0xd8> + 104ac: 00892423 sw s0,8(s2) + 104b0: fa1ff06f j 10450 <__call_exitprocs+0xb8> + 104b4: 00058513 mv a0,a1 + 104b8: 000700e7 jalr a4 + 104bc: fb5ff06f j 10470 <__call_exitprocs+0xd8> + +00000000000104c0 <__libc_fini_array>: + 104c0: fe010113 addi sp,sp,-32 + 104c4: 00813823 sd s0,16(sp) + 104c8: 000117b7 lui a5,0x11 + 104cc: 00011437 lui s0,0x11 + 104d0: 62878793 addi a5,a5,1576 # 11628 <__do_global_dtors_aux_fini_array_entry> + 104d4: 63040413 addi s0,s0,1584 # 11630 + 104d8: 40f40433 sub s0,s0,a5 + 104dc: 00913423 sd s1,8(sp) + 104e0: 00113c23 sd ra,24(sp) + 104e4: 40345493 srai s1,s0,0x3 + 104e8: 02048063 beqz s1,10508 <__libc_fini_array+0x48> + 104ec: ff840413 addi s0,s0,-8 + 104f0: 00f40433 add s0,s0,a5 + 104f4: 00043783 ld a5,0(s0) + 104f8: fff48493 addi s1,s1,-1 + 104fc: ff840413 addi s0,s0,-8 + 10500: 000780e7 jalr a5 + 10504: fe0498e3 bnez s1,104f4 <__libc_fini_array+0x34> + 10508: 01813083 ld ra,24(sp) + 1050c: 01013403 ld s0,16(sp) + 10510: 00813483 ld s1,8(sp) + 10514: 02010113 addi sp,sp,32 + 10518: 00008067 ret + +000000000001051c : + 1051c: 00050593 mv a1,a0 + 10520: 00000693 li a3,0 + 10524: 00000613 li a2,0 + 10528: 00000513 li a0,0 + 1052c: 0040006f j 10530 <__register_exitproc> + +0000000000010530 <__register_exitproc>: + 10530: f481b703 ld a4,-184(gp) # 11d78 <_global_impure_ptr> + 10534: 1f873783 ld a5,504(a4) + 10538: 06078063 beqz a5,10598 <__register_exitproc+0x68> + 1053c: 0087a703 lw a4,8(a5) + 10540: 01f00813 li a6,31 + 10544: 08e84663 blt a6,a4,105d0 <__register_exitproc+0xa0> + 10548: 02050863 beqz a0,10578 <__register_exitproc+0x48> + 1054c: 00371813 slli a6,a4,0x3 + 10550: 01078833 add a6,a5,a6 + 10554: 10c83823 sd a2,272(a6) + 10558: 3107a883 lw a7,784(a5) + 1055c: 00100613 li a2,1 + 10560: 00e6163b sllw a2,a2,a4 + 10564: 00c8e8b3 or a7,a7,a2 + 10568: 3117a823 sw a7,784(a5) + 1056c: 20d83823 sd a3,528(a6) + 10570: 00200693 li a3,2 + 10574: 02d50863 beq a0,a3,105a4 <__register_exitproc+0x74> + 10578: 00270693 addi a3,a4,2 + 1057c: 00369693 slli a3,a3,0x3 + 10580: 0017071b addiw a4,a4,1 + 10584: 00e7a423 sw a4,8(a5) + 10588: 00d787b3 add a5,a5,a3 + 1058c: 00b7b023 sd a1,0(a5) + 10590: 00000513 li a0,0 + 10594: 00008067 ret + 10598: 20070793 addi a5,a4,512 + 1059c: 1ef73c23 sd a5,504(a4) + 105a0: f9dff06f j 1053c <__register_exitproc+0xc> + 105a4: 3147a683 lw a3,788(a5) + 105a8: 00000513 li a0,0 + 105ac: 00c6e6b3 or a3,a3,a2 + 105b0: 30d7aa23 sw a3,788(a5) + 105b4: 00270693 addi a3,a4,2 + 105b8: 00369693 slli a3,a3,0x3 + 105bc: 0017071b addiw a4,a4,1 + 105c0: 00e7a423 sw a4,8(a5) + 105c4: 00d787b3 add a5,a5,a3 + 105c8: 00b7b023 sd a1,0(a5) + 105cc: 00008067 ret + 105d0: fff00513 li a0,-1 + 105d4: 00008067 ret + +00000000000105d8 <_exit>: + 105d8: 05d00893 li a7,93 + 105dc: 00000073 ecall + 105e0: 00054463 bltz a0,105e8 <_exit+0x10> + 105e4: 0000006f j 105e4 <_exit+0xc> + 105e8: ff010113 addi sp,sp,-16 + 105ec: 00813023 sd s0,0(sp) + 105f0: 00050413 mv s0,a0 + 105f4: 00113423 sd ra,8(sp) + 105f8: 4080043b negw s0,s0 + 105fc: 00c000ef jal ra,10608 <__errno> + 10600: 00852023 sw s0,0(a0) + 10604: 0000006f j 10604 <_exit+0x2c> + +0000000000010608 <__errno>: + 10608: f581b503 ld a0,-168(gp) # 11d88 <_impure_ptr> + 1060c: 00008067 ret + +Disassembly of section .eh_frame: + +0000000000011610 <__FRAME_END__>: + 11610: 0000 .2byte 0x0 + ... + +Disassembly of section .init_array: + +0000000000011618 <__init_array_start>: + 11618: 0118 .2byte 0x118 + 1161a: 0001 .2byte 0x1 + 1161c: 0000 .2byte 0x0 + ... + +0000000000011620 <__frame_dummy_init_array_entry>: + 11620: 01c0 .2byte 0x1c0 + 11622: 0001 .2byte 0x1 + 11624: 0000 .2byte 0x0 + ... + +Disassembly of section .fini_array: + +0000000000011628 <__do_global_dtors_aux_fini_array_entry>: + 11628: 017c .2byte 0x17c + 1162a: 0001 .2byte 0x1 + 1162c: 0000 .2byte 0x0 + ... + +Disassembly of section .data: + +0000000000011630 : + ... + 11638: 1b68 .2byte 0x1b68 + 1163a: 0001 .2byte 0x1 + 1163c: 0000 .2byte 0x0 + 1163e: 0000 .2byte 0x0 + 11640: 1c18 .2byte 0x1c18 + 11642: 0001 .2byte 0x1 + 11644: 0000 .2byte 0x0 + 11646: 0000 .2byte 0x0 + 11648: 1cc8 .2byte 0x1cc8 + 1164a: 0001 .2byte 0x1 + ... + 11718: 0001 .2byte 0x1 + 1171a: 0000 .2byte 0x0 + 1171c: 0000 .2byte 0x0 + 1171e: 0000 .2byte 0x0 + 11720: 330e .2byte 0x330e + 11722: abcd .2byte 0xabcd + 11724: 1234 .2byte 0x1234 + 11726: e66d .2byte 0xe66d + 11728: deec .2byte 0xdeec + 1172a: 0005 .2byte 0x5 + 1172c: 0000000b .4byte 0xb + ... + +Disassembly of section .sdata: + +0000000000011d78 <_global_impure_ptr>: + 11d78: 1630 .2byte 0x1630 + 11d7a: 0001 .2byte 0x1 + 11d7c: 0000 .2byte 0x0 + ... + +0000000000011d80 <__dso_handle>: + ... + +0000000000011d88 <_impure_ptr>: + 11d88: 1630 .2byte 0x1630 + 11d8a: 0001 .2byte 0x1 + 11d8c: 0000 .2byte 0x0 + ... + +Disassembly of section .bss: + +0000000000011d90 : + ... + +0000000000011d98 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 .2byte 0x2820 + 6: 2029 .2byte 0x2029 + 8: 3231 .2byte 0x3231 + a: 322e .2byte 0x322e + c: 302e .2byte 0x302e + e: 4700 .2byte 0x4700 + 10: 203a4343 .4byte 0x203a4343 + 14: 4728 .2byte 0x4728 + 16: 554e .2byte 0x554e + 18: 2029 .2byte 0x2029 + 1a: 3231 .2byte 0x3231 + 1c: 322e .2byte 0x322e + 1e: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 2041 .2byte 0x2041 + 2: 0000 .2byte 0x0 + 4: 7200 .2byte 0x7200 + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 + c: 0016 .2byte 0x16 + e: 0000 .2byte 0x0 + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f30 .2byte 0x5f30 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + ... diff --git a/memory.txt b/memory.txt index 905bcdb..d09a7fe 100644 --- a/memory.txt +++ b/memory.txt @@ -1,8 +1,8 @@ -4000 1b8 +1b8 4000 ffffff97 ffffffd0 0000003f 00000000 ffffffe7 ffffff80 00000000 00000041 00000013 00000005 00000000 00000000 ffffffef 00000000 00000040 00000001 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000000 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000010 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000020 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000030 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000040 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000050 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000060 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000070 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffff80 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffff90 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 fffffff0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffa0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffe0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffb0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffc0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffd0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffe0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 fffffff0 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000000 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000000 00000002 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000010 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000020 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000030 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000040 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000050 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000060 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000070 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffff80 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffff90 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffa0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffb0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffc0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 ffffffd0 00000001 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000010 00000002 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000020 00000002 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -400000 1450 +1450 400000 00000013 00000001 00000001 fffffffd 00000023 00000034 00000011 00000002 00000023 00000030 ffffff81 00000002 00000013 00000004 00000001 00000003 00000023 0000003c ffffffa4 fffffffc ffffff83 00000037 ffffff84 fffffffd 00000023 00000034 fffffff4 fffffffe ffffff83 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00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 ffffffd0 0000000f 00000040 00000000 -P4000 -S405270 \ No newline at end of file +4000 +405270 diff --git a/old_section.txt b/old_section.txt new file mode 100644 index 0000000..21571c8 --- /dev/null +++ b/old_section.txt @@ -0,0 +1,17 @@ +fe010113 +00813c23 +02010413 +fe042623 +00100793 +fef42423 +fec42783 +00078713 +fe842783 +00f707bb +fef42623 +00000013 +01813403 +02010113 +00008067 +0 +0 \ No newline at end of file From fd982583240fda3f42183a93810e06bd5334aaf1 Mon Sep 17 00:00:00 2001 From: amaury Date: Thu, 2 Mar 2023 15:51:00 +0100 Subject: [PATCH 102/128] nouveau fichier memoire avec swap des octets --- memory.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/memory.txt b/memory.txt index d09a7fe..114b58f 100644 --- a/memory.txt +++ b/memory.txt @@ -1,8 +1,8 @@ -1b8 4000 -ffffff97 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05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 fe 04 26 23 00 10 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 4000 -405270 +405270 \ No newline at end of file From 6072ba97d60da524c99d905db201d50f6df8550a Mon Sep 17 00:00:00 2001 From: Baptiste Date: Fri, 3 Mar 2023 12:21:37 +0100 Subject: [PATCH 103/128] update memory --- memory.txt | 6 +++--- src/simulator/mem_cmp.rs | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/memory.txt b/memory.txt index d09a7fe..6eeebc3 100644 --- a/memory.txt +++ b/memory.txt @@ -1,8 +1,8 @@ -1b8 4000 +4000 1b8 ffffff97 ffffffd0 0000003f 00000000 ffffffe7 ffffff80 00000000 00000041 00000013 00000005 00000000 00000000 ffffffef 00000000 00000040 00000001 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000000 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000010 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000020 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000030 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000040 00000000 00000073 00000000 00000000 00000000 00000067 ffffff80 00000000 00000000 ffffff93 00000008 00000050 00000000 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00000005 00000000 00000023 0000002a fffffff4 fffffffc ffffff93 00000007 00000004 00000003 00000023 00000030 fffffff4 fffffffc ffffff83 00000037 00000004 fffffffc ffffff93 ffffff87 ffffff87 fffffffd 00000023 00000034 fffffff4 fffffffe 00000003 00000037 ffffff84 fffffffe ffffff83 00000027 00000044 fffffffd ffffff93 00000006 00000007 00000000 00000003 00000036 ffffff84 fffffffc ffffff93 ffffff85 00000007 00000000 00000003 00000035 ffffff84 fffffffd ffffffef fffffff0 ffffff8f ffffffdd ffffff93 00000007 00000005 00000000 00000023 0000002a fffffff4 fffffffc ffffff83 00000027 00000044 fffffffd 00000013 ffffff85 00000007 00000000 ffffff83 00000030 ffffff81 00000003 00000003 00000034 00000001 00000003 00000013 00000001 00000001 00000007 00000067 ffffff80 00000000 00000000 00000013 00000001 00000001 ffffffec 00000023 0000003c 00000011 0000000e 00000023 00000038 ffffff81 0000000e 00000013 00000004 00000001 00000010 00000023 00000034 ffffffa4 fffffff0 00000023 00000034 ffffffb4 00000000 00000023 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00000063 00000050 fffffff0 00000002 00000003 00000027 ffffffc4 fffffffe ffffff93 00000007 ffffff84 fffffff1 00000013 00000006 00000010 00000000 ffffff93 00000005 00000007 00000000 00000013 ffffff85 00000007 00000000 ffffff97 00000030 ffffffc0 ffffffff ffffffe7 ffffff80 00000000 ffffffcc 00000013 00000000 00000000 00000000 ffffff83 00000030 ffffff81 0000000f 00000003 00000034 00000001 0000000f 00000013 00000001 00000001 00000014 00000067 ffffff80 00000000 00000000 00000013 00000001 00000001 fffffff2 00000023 0000003c 00000011 0000000c 00000023 00000038 ffffff81 0000000c 00000013 00000004 00000001 0000000e ffffff93 00000007 ffffff84 fffffff2 00000013 00000006 00000000 00000000 ffffff93 00000005 ffffff80 0000000c 00000013 ffffff85 00000007 00000000 ffffff97 00000030 ffffffc0 ffffffff ffffffe7 ffffff80 ffffff80 ffffffc7 ffffff93 00000007 ffffff84 fffffff2 00000013 ffffff85 00000007 00000000 ffffffef ffffffe0 ffffff9f ffffffff ffffff93 00000007 00000005 00000000 00000013 ffffff85 00000007 00000000 ffffff83 00000030 ffffff81 0000000d 00000003 00000034 00000001 0000000d 00000013 00000001 00000001 0000000e 00000067 ffffff80 00000000 00000000 00000013 00000001 00000001 fffffffe 00000023 0000003c ffffff81 00000000 00000013 00000004 00000001 00000002 00000023 00000026 00000004 fffffffe ffffff93 00000007 00000010 00000000 00000023 00000024 fffffff4 fffffffe ffffff83 00000027 ffffffc4 fffffffe 00000013 ffffff87 00000007 00000000 ffffff83 00000027 ffffff84 fffffffe ffffffbb 00000007 fffffff7 00000000 00000023 00000026 fffffff4 fffffffe ffffff93 00000007 00000000 00000000 00000013 ffffff85 00000007 00000000 00000003 00000034 ffffff81 00000001 00000013 00000001 00000001 00000002 00000067 ffffff80 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -80 404000 +404000 80 00000025 00000078 00000009 00000000 00000000 00000000 00000000 00000000 00000020 00000020 00000020 00000000 00000000 00000000 00000000 00000000 00000025 00000073 00000020 00000000 00000000 00000000 00000000 00000000 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000028 0000006e 00000075 0000006c 0000006c 00000029 00000000 00000000 fffffff8 0000000e 00000040 00000000 ffffffe8 00000009 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 ffffffe8 00000009 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 00000028 0000000b 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000004c 0000000f 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 0000007c 00000011 00000040 00000000 ffffffd0 0000000f 00000040 00000000 4000 405270 diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index e90fec7..94aac44 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -75,8 +75,8 @@ impl Section{ fn print_Section(s: &Section){ - println!("ADDR :: {}", s.addr); - println!("LEN :: {}", s.len); + println!("ADDR :: {:x}", s.addr); + println!("LEN :: {:x}", s.len); println!("CONTENT :: {:?}", s.content); } } From 6f6191ea3ccf79b48e55dd402536853f4fdf2810 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Sun, 5 Mar 2023 23:49:28 +0100 Subject: [PATCH 104/128] memory.txt can be execute --- src/main.rs | 4 ++-- src/simulator/machine.rs | 24 ++++++++++++++++++------ src/simulator/mem_cmp.rs | 1 + src/simulator/print.rs | 4 ++-- 4 files changed, 23 insertions(+), 10 deletions(-) diff --git a/src/main.rs b/src/main.rs index 6e4d2c7..bc3da12 100644 --- a/src/main.rs +++ b/src/main.rs @@ -8,7 +8,7 @@ fn main() { let path = "memory.txt".to_string(); let checker = mem_cmp::Mem_Checker::from(&path); mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); - mem_cmp::Mem_Checker::print_Mem_Checker(&checker); - Machine::print_memory(&mut m, 0x400000, 0x405000); + //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); + //Machine::print_memory(&mut m, 0x400000, 0x405000); Machine::run(m); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index bd5617a..c3a5659 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -1,5 +1,7 @@ use std::{ops::{Add, Sub}, io::Write}; +use crate::simulator::print; + use super::{decode::{Instruction, decode}}; use super::global::*; use std::fs::File; @@ -40,7 +42,7 @@ impl Register { self.register[position] = value; } else { // Panic ou rien ? (dans le doute pour le moment panic) - unreachable!("You can't write to zero register") + // unreachable!("You can't write to zero register") } } @@ -148,6 +150,14 @@ impl Machine { file.write(&machine.main_memory); } + pub fn print_machine_status(machine: &mut Machine) { + println!("######### Machine status #########"); + for i in 0..32 { + println!(">{} : {:x}", print::REG_X[i], machine.int_reg.get_reg(i)); + } + println!("##################################"); + } + /// Execute the instructions table of a machine putted in param /// /// ### Parameters @@ -182,13 +192,15 @@ impl Machine { if machine.main_memory.len() <= machine.pc as usize { panic!("ERROR : number max of instructions rushed"); } - let mut val: [u8; 8] = [0; 8]; - for i in 0..8 { + let mut val: [u8; 4] = [0; 4]; + for i in 0..4 { val[i] = machine.main_memory[machine.pc as usize + i]; } - let val = u64::from_be_bytes(val); - println!("{:x}", val); + let val = u32::from_be_bytes(val) as u64; + Self::print_machine_status(machine); + println!("executing instruction : {:016x} at pc {:x}", val, machine.pc); + println!("{}", print::print(decode(val), machine.pc as i32)); let inst : Instruction = decode(val); @@ -602,7 +614,7 @@ impl Machine { } } } - _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, + _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, } machine.pc += 4; // Possible bug avec jump diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 94aac44..316df70 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -160,6 +160,7 @@ impl Mem_Checker{ pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ machine.sp = m_c.sp; + machine.int_reg.set_reg(2, m_c.pc as i64); machine.pc = m_c.pc as u64; diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 0539a43..60a2936 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -13,7 +13,7 @@ const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; // Register name mapping -const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", +pub const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"]; @@ -78,7 +78,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed)) }, RISCV_JALR => { - format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) + format!("jalr\t{},{:x}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_BR => { format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32)) From cef082bfd5c015b206724e64ae0fe9fd5a2bb1dd Mon Sep 17 00:00:00 2001 From: amaury Date: Mon, 6 Mar 2023 11:19:00 +0100 Subject: [PATCH 105/128] =?UTF-8?q?ajout=20des=20m=C3=A9moires=20nachos=20?= =?UTF-8?q?de=20tous=20les=20tests?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- memoryComp.txt | 8 ++++++++ memoryDiv.txt | 8 ++++++++ memoryIf.txt | 8 ++++++++ memoryJump.txt | 8 ++++++++ memoryMul.txt | 8 ++++++++ memoryRet.txt | 8 ++++++++ memorySub.txt | 8 ++++++++ memorySwitch.txt | 8 ++++++++ src/main.rs | 2 +- 9 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 memoryComp.txt create mode 100644 memoryDiv.txt create mode 100644 memoryIf.txt create mode 100644 memoryJump.txt create mode 100644 memoryMul.txt create mode 100644 memoryRet.txt create mode 100644 memorySub.txt create mode 100644 memorySwitch.txt diff --git a/memoryComp.txt b/memoryComp.txt new file mode 100644 index 0000000..0d30a7a --- /dev/null +++ b/memoryComp.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 00 00 00 73 00 00 80 67 01 30 08 93 00 00 00 73 00 00 80 67 01 40 08 93 00 00 00 73 00 00 80 67 01 50 08 93 00 00 00 73 00 00 80 67 01 60 08 93 00 00 00 73 00 00 80 67 01 70 08 93 00 00 00 73 00 00 80 67 01 80 08 93 00 00 00 73 00 00 80 67 01 90 08 93 00 00 00 73 00 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22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 fe 04 26 23 00 10 07 93 fe f4 24 23 08 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 00 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+405270 \ No newline at end of file diff --git a/memoryDiv.txt b/memoryDiv.txt new file mode 100644 index 0000000..682294e --- /dev/null +++ b/memoryDiv.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 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24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 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27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 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f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 40 07 93 fe f4 26 23 00 20 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 02 f7 57 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memoryIf.txt b/memoryIf.txt new file mode 100644 index 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c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 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27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 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00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 10 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 00 10 07 93 00 f7 1e 63 fe c4 27 83 00 07 87 9b 00 f0 58 63 00 20 07 93 fe f4 26 23 02 c0 00 6f fe c4 27 83 00 07 87 9b 00 07 98 63 fe c4 27 83 00 07 87 9b 00 07 98 63 00 30 07 93 fe f4 26 23 00 80 00 6f fe 04 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memoryJump.txt b/memoryJump.txt new file mode 100644 index 0000000..86ec072 --- /dev/null +++ b/memoryJump.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 43 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 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84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 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00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 ff 01 01 13 00 81 34 23 01 01 04 13 00 00 07 93 00 07 85 13 00 81 34 03 01 01 01 13 00 00 80 67 fe 01 01 13 00 11 3c 23 00 81 38 23 02 01 04 13 fd 1f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memoryMul.txt b/memoryMul.txt new file mode 100644 index 0000000..b8b038c --- /dev/null +++ b/memoryMul.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 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80 67 fe 01 01 13 00 11 3c 23 00 81 38 23 02 01 04 13 fe a4 34 23 fe b4 30 23 00 40 07 b7 00 07 87 93 00 07 87 9b fe 04 37 03 00 07 07 1b 00 07 06 13 00 07 85 93 fe 84 35 03 ff c0 40 97 01 c0 80 e7 00 05 07 93 00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 24 23 fe 04 22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 10 07 93 fe f4 26 23 00 20 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 02 f7 07 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memoryRet.txt b/memoryRet.txt new file mode 100644 index 0000000..2046f06 --- /dev/null +++ b/memoryRet.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 00 00 00 73 00 00 80 67 01 30 08 93 00 00 00 73 00 00 80 67 01 40 08 93 00 00 00 73 00 00 80 67 01 50 08 93 00 00 00 73 00 00 80 67 01 60 08 93 00 00 00 73 00 00 80 67 01 70 08 93 00 00 00 73 00 00 80 67 01 80 08 93 00 00 00 73 00 00 80 67 01 90 08 93 00 00 00 73 00 00 80 67 01 a0 08 93 00 00 00 73 00 00 80 67 01 b0 08 93 00 00 00 73 00 00 80 67 01 c0 08 93 00 00 00 73 00 00 80 67 01 d0 08 93 00 00 00 73 00 00 80 67 02 10 08 93 00 00 00 73 00 00 80 67 02 20 08 93 00 00 00 73 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +400000 1430 +fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fd 84 37 83 fe f4 34 23 fe 84 37 83 00 07 80 e7 00 00 05 13 ff c0 40 97 ff 80 80 e7 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 11 3c 23 00 81 38 23 02 01 04 13 fe a4 34 23 fe b4 30 23 00 40 07 b7 00 07 87 93 00 07 87 9b fe 04 37 03 00 07 07 1b 00 07 06 13 00 07 85 93 fe 84 35 03 ff c0 40 97 01 c0 80 e7 00 05 07 93 00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 24 23 fe 04 22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 ff 01 01 13 00 81 34 23 01 01 04 13 00 10 07 93 00 07 85 13 00 81 34 03 01 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memorySub.txt b/memorySub.txt new file mode 100644 index 0000000..9cf1238 --- /dev/null +++ b/memorySub.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 00 00 00 73 00 00 80 67 01 30 08 93 00 00 00 73 00 00 80 67 01 40 08 93 00 00 00 73 00 00 80 67 01 50 08 93 00 00 00 73 00 00 80 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00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 24 23 fe 04 22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 10 07 93 fe f4 26 23 00 10 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/memorySwitch.txt b/memorySwitch.txt new file mode 100644 index 0000000..3bd6096 --- /dev/null +++ b/memorySwitch.txt @@ -0,0 +1,8 @@ +4000 1b8 +00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 00 00 00 73 00 00 80 67 01 30 08 93 00 00 00 73 00 00 80 67 01 40 08 93 00 00 00 73 00 00 80 67 01 50 08 93 00 00 00 73 00 00 80 67 01 60 08 93 00 00 00 73 00 00 80 67 01 70 08 93 00 00 00 73 00 00 80 67 01 80 08 93 00 00 00 73 00 00 80 67 01 90 08 93 00 00 00 73 00 00 80 67 01 a0 08 93 00 00 00 73 00 00 80 67 01 b0 08 93 00 00 00 73 00 00 80 67 01 c0 08 93 00 00 00 73 00 00 80 67 01 d0 08 93 00 00 00 73 00 00 80 67 02 10 08 93 00 00 00 73 00 00 80 67 02 20 08 93 00 00 00 73 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +400000 1458 +fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fd 84 37 83 fe f4 34 23 fe 84 37 83 00 07 80 e7 00 00 05 13 ff c0 40 97 ff 80 80 e7 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 11 3c 23 00 81 38 23 02 01 04 13 fe a4 34 23 fe b4 30 23 00 40 07 b7 00 07 87 93 00 07 87 9b fe 04 37 03 00 07 07 1b 00 07 06 13 00 07 85 93 fe 84 35 03 ff c0 40 97 01 c0 80 e7 00 05 07 93 00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 24 23 fe 04 22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 1b 00 70 07 93 ec e7 f0 e3 fb 84 27 83 00 07 87 9b 0c 07 90 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 fe 04 26 23 fe c4 27 83 00 07 87 1b 00 10 07 93 00 f7 1c 63 00 10 07 93 fe f4 26 23 00 00 00 13 00 00 07 93 00 80 00 6f 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +404000 80 +00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 +4000 +405270 \ No newline at end of file diff --git a/src/main.rs b/src/main.rs index bc3da12..d33c4dc 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,7 +5,7 @@ use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); - let path = "memory.txt".to_string(); + let path = "memoryComp.txt".to_string(); let checker = mem_cmp::Mem_Checker::from(&path); mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); From abff8966b5e033159cee940db55763d9d8c0370c Mon Sep 17 00:00:00 2001 From: amaury Date: Mon, 6 Mar 2023 11:37:16 +0100 Subject: [PATCH 106/128] nouveau fichier de comparaisons --- .../boolean_logic/new_comparisons.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 test_programs/riscv_instructions/boolean_logic/new_comparisons.c diff --git a/test_programs/riscv_instructions/boolean_logic/new_comparisons.c b/test_programs/riscv_instructions/boolean_logic/new_comparisons.c new file mode 100644 index 0000000..54bd275 --- /dev/null +++ b/test_programs/riscv_instructions/boolean_logic/new_comparisons.c @@ -0,0 +1,17 @@ +int main() { + int x = 0; + int y = 1; + while (x <= y) { + if (x > y) { + y += 1; + } + if (x == y) { + x += y; + } + if (x < y) { + x += 1; + } else { + return 0; + } + } +} \ No newline at end of file From d352f5dcd2f0dfa1cc698d452e9e0c00fd896692 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Mon, 6 Mar 2023 13:50:45 +0100 Subject: [PATCH 107/128] fix jal, branch instr & LD. + better print for machine status --- src/main.rs | 2 +- src/simulator/machine.rs | 34 +++++++++++++++++++++++----------- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/main.rs b/src/main.rs index d33c4dc..2acab96 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,7 +5,7 @@ use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); - let path = "memoryComp.txt".to_string(); + let path = "memoryJump.txt".to_string(); let checker = mem_cmp::Mem_Checker::from(&path); mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index c3a5659..2baf432 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -152,9 +152,21 @@ impl Machine { pub fn print_machine_status(machine: &mut Machine) { println!("######### Machine status #########"); - for i in 0..32 { - println!(">{} : {:x}", print::REG_X[i], machine.int_reg.get_reg(i)); + for i in (0..32).step_by(3) { + print!(">{0: <4} : {1:<8x}", print::REG_X[i], machine.int_reg.get_reg(i)); + print!("\t"); + print!(">{0: <4} : {1:<8x}", print::REG_X[i+1], machine.int_reg.get_reg(i+1)); + print!("\t"); + if i+2 < 32 { + print!(">{0: <4} : {1:<8x}", print::REG_X[i+2], machine.int_reg.get_reg(i+2)); + } + println!(); } + println!("________________SP________________"); + let sp_index = machine.int_reg.get_reg(2); + for i in 0..5 { + println!("SP+{:<2} : {:16x}", i*8, Self::read_memory(machine, 8, (sp_index + i*8) as usize)); + } println!("##################################"); } @@ -213,11 +225,11 @@ impl Machine { }, RISCV_JAL => { machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); - machine.pc += inst.imm21_1_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; machine.int_reg.set_reg(inst.rd as usize, tmp as i64); }, @@ -227,32 +239,32 @@ impl Machine { match inst.funct3 { RISCV_BR_BEQ => { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BNE => { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLT => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGE => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLTU => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGEU => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, _ => { @@ -278,7 +290,7 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LD => { - let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, _ => { From 1e2e537ec99bc0d8babb3e7720598b990a260ae2 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Tue, 7 Mar 2023 17:32:59 +0100 Subject: [PATCH 108/128] compare mem_checker and machine --- src/main.rs | 2 +- src/simulator/machine.rs | 17 +++++++++++------ src/simulator/mem_cmp.rs | 13 +++++++++++++ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/src/main.rs b/src/main.rs index 2acab96..97c0ec1 100644 --- a/src/main.rs +++ b/src/main.rs @@ -10,5 +10,5 @@ fn main() { mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); //Machine::print_memory(&mut m, 0x400000, 0x405000); - Machine::run(m); + //Machine::run(m); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 2baf432..47ee672 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -177,9 +177,7 @@ impl Machine { /// - **machine** which contains a table of instructions pub fn run(machine : Machine){ let mut m = machine; - for i in 0..MEM_SIZE{ - Machine::one_instruction(&mut m); - } + while Machine::one_instruction(&mut m) == 0 {} } /// execute the current instruction @@ -187,7 +185,7 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions and a pc to the actual instruction - pub fn one_instruction(machine :&mut Machine) { + pub fn one_instruction(machine :&mut Machine) -> i32 { let unsigned_reg1 : u64; let unsigned_reg2 : u64; @@ -210,10 +208,11 @@ impl Machine { } let val = u32::from_be_bytes(val) as u64; + let inst : Instruction = decode(val); Self::print_machine_status(machine); println!("executing instruction : {:016x} at pc {:x}", val, machine.pc); println!("{}", print::print(decode(val), machine.pc as i32)); - let inst : Instruction = decode(val); + match inst.opcode { @@ -626,10 +625,16 @@ impl Machine { } } } + RISCV_SYSTEM => { + // temporary return value to stop the loop of run + // before we can use system call + return 1; + } _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, } - machine.pc += 4; // Possible bug avec jump + machine.pc += 4; + return 0; } diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 316df70..e1cb7e4 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -194,6 +194,19 @@ impl Mem_Checker{ } + pub fn compare_machine_memory(m_c: &Mem_Checker, machine: &Machine) -> bool { + + for section in m_c.sections.iter() { + for i in 0..section.len { + if machine.main_memory[section.addr + i] != section.content[i] { + return false; + } + } + } + + return true; + } + } From da30122c87126f0068fa4702d5b7577418998119 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 8 Mar 2023 11:15:13 +0100 Subject: [PATCH 109/128] Added documentation for from function --- src/simulator/mem_cmp.rs | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index e1cb7e4..febe371 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -93,6 +93,15 @@ pub struct Mem_Checker{ impl Mem_Checker{ + ///Translate lines of a file in e Vector of String + ///We need this method to parse the memory we received + /// + /// ### Parameters + /// + /// - **Lines** The file to parse + /// + /// ### Return + /// - A vector of String where each line of the file os an element of the vector fn vect_from_lines(lines: &mut Lines>, pc: &mut usize, sp: &mut usize) -> Vec{ let mut vector = Vec::new(); for (i,line) in lines.enumerate() { @@ -104,6 +113,14 @@ impl Mem_Checker{ vector } + /// Fill a mem checker from a file (here the mock memory) + /// Extract the values of pc, sp and sections + /// + /// ### Parameter + /// -**path** addr to the file + /// + /// ### Return + /// Mem-checker filled pub fn from(path: &String) -> Mem_Checker { let file = fs::File::open(path).expect("Wrong filename"); @@ -146,6 +163,11 @@ impl Mem_Checker{ } + /// Print the content of a Mem_Checker + /// + /// ### Parameter + /// + /// - **m_c** Contains the data we want to print pub fn print_Mem_Checker(m_c: &Mem_Checker){ println!("PC :: {:x}", m_c.pc); println!("SP :: {:x}", m_c.sp); @@ -157,6 +179,12 @@ impl Mem_Checker{ } + /// Fill a machine's memory from a Mem Chacker + /// + /// ### Parameters + /// + /// - **m_c** contains the data + /// - **machine** contains the memry to fill pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ machine.sp = m_c.sp; From 90e51149af1be0b8f4584cd705cd04213e4f5a3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 13:00:38 +0100 Subject: [PATCH 110/128] Added libnachos --- test_programs/userlib/Makefile | 4 + test_programs/userlib/ldscript.lds | 61 +++ test_programs/userlib/libnachos.c | 630 +++++++++++++++++++++++++++++ test_programs/userlib/libnachos.h | 87 ++++ test_programs/userlib/sys.s | 343 ++++++++++++++++ test_programs/userlib/syscall.h | 287 +++++++++++++ 6 files changed, 1412 insertions(+) create mode 100644 test_programs/userlib/Makefile create mode 100644 test_programs/userlib/ldscript.lds create mode 100644 test_programs/userlib/libnachos.c create mode 100644 test_programs/userlib/libnachos.h create mode 100644 test_programs/userlib/sys.s create mode 100644 test_programs/userlib/syscall.h diff --git a/test_programs/userlib/Makefile b/test_programs/userlib/Makefile new file mode 100644 index 0000000..903f3b5 --- /dev/null +++ b/test_programs/userlib/Makefile @@ -0,0 +1,4 @@ +TOPDIR = ../ +include $(TOPDIR)/Makefile.tests + +default: sys.o libnachos.o \ No newline at end of file diff --git a/test_programs/userlib/ldscript.lds b/test_programs/userlib/ldscript.lds new file mode 100644 index 0000000..7bc9ebf --- /dev/null +++ b/test_programs/userlib/ldscript.lds @@ -0,0 +1,61 @@ +/* + ldscript for running user programs under Nachos + + Sections should be aligned on page boundaries. Here an alignement of + at least 0x2000 is selected, thus supporting pages up to 8KB + large. See addrspace.cc for details. +*/ + +ENTRY(__start) +SECTIONS +{ + + /* Skip an area of about 8k, so that NULL pointer dereferences can + be detected */ + . += 0x2000; + + .sys ALIGN(0x4000) : { + *(.init) + *(.sys) + } + + /* Code is aligned on a 16k boundary + Due to the size of the .sys section, the code start address will + presumably be at address 0x4000 */ + .text ALIGN(0x400000) : { + _ftext = .; + eprol = .; + *(.text) + *(.fini) + } + etext = .; + _etext = .; + + /* Initialized data is aligned on a 16k boundary */ + .data ALIGN(0x4000) : { + _fdata = .; + *(.data) + *(.sdata) + } + .rodata ALIGN(0x4000) : + { + *(.rdata) + *(.srodata) + *(.rodata) + } + edata = .; + _edata = .; + + /* Non-initialized data is aligned on a 16k boundary */ + /* Bss = Block Started by Symbol */ + .bss ALIGN(0x4000) : { + *(.bss) + *(.sbss) + *(.scommon) + *(COMMON) + } + + end = .; + _end = .; + +} diff --git a/test_programs/userlib/libnachos.c b/test_programs/userlib/libnachos.c new file mode 100644 index 0000000..32bb273 --- /dev/null +++ b/test_programs/userlib/libnachos.c @@ -0,0 +1,630 @@ +/*! \file libnachos.c + * \brief Functions of our library, for user programs. + * + * This library only provides some usefull functions for + * programming. + * + * ----------------------------------------------------- + * This file is part of the Nachos-RiscV distribution + * Copyright (c) 2022 University of Rennes 1. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details + * (see see ). + * ----------------------------------------------------- + */ + +#include "libnachos.h" +#include +#include + +//---------------------------------------------------------------------- +// threadStart() +/*! Makes a thread execute a function or program. This function +// is static, it is called internally by library function threadCreate +// and should not be called directly by user programs. The interest +// of this function is to be able to terminate threads correctly, +// even when the thread to be terminated does not explicitly call +// Exit. threadStart provides the mechanism by which Exit +// is called automatically +// +// \param func is the identificator of the function to execute. +*/ +//---------------------------------------------------------------------- + +static void threadStart(uint64_t func) +{ + VoidNoArgFunctionPtr func2; + func2=(VoidNoArgFunctionPtr)func; + // Call the function that actually contains the thread code + (*func2)(); + // Call exit, such that there is no return using an empty stack + Exit(0); +} + +//---------------------------------------------------------------------- +// threadCreate() +/*! Creates a thread and makes it execute a function. +// +// NB : instead of directly executing the required function, +// function threadStart is called so as to ensure +// that the thread will properly exit +// This function must be called instead of calling directly +// the system call newThread +// +// \param name the name of the thread (for debugging purpose) +// \param func is the address of the function to execute. +*/ +//---------------------------------------------------------------------- +ThreadId threadCreate(char *debug_name, VoidNoArgFunctionPtr func) +{ + return newThread(debug_name, (uint64_t)threadStart,(uint64_t)func); +} + +//---------------------------------------------------------------------- +// n_strcmp() +/*! String comparison +// +// \param s1 is the first string, +// \param s2 is the second one. +// \return an integer greater than, equal to, or less than 0, +// if the first string is greater than, equal to, or less than +// the the second string. +*/ +//---------------------------------------------------------------------- +int n_strcmp(const char *s1, const char *s2) +{ + int comparaison; + int fini=0; + int i=0; + while(!fini) { + if ((s1[i]==0)&&(s2[i]==0)) { + fini=1; + comparaison=0; + } + if (s1[i]s2[i]) { + fini=1; + comparaison=1; + } + i++; + } + return comparaison; +} + +//---------------------------------------------------------------------- +// n_strcpy() +/*! String copy +// +// \param dst is where the string is to be copied, +// \param src is where the string to copy is. +// \return dst, if the copy successes, 0 otherwise +*/ +//---------------------------------------------------------------------- +char *n_strcpy(char *dst, const char *src) +{ + int i=0; + int fini=0; + if ((dst!=0)&&(src!=0)) { + while(fini==0) { + if(src[i]=='\0') fini=1; + dst[i]=src[i]; + i++; + } + return dst; + } + else return 0; +} + +//---------------------------------------------------------------------- +// n_strlen() +/*! Gives the number of bytes in a string, not including the +// terminating null character. +// +// \param c is a pointer onto a string. +// \return the length of the string. +*/ +//---------------------------------------------------------------------- +size_t n_strlen(const char *s) +{ + size_t i=0; + while (s[i] != 0) i++; + return i; +} + + +//---------------------------------------------------------------------- +// n_strcat() +/*! Appends a copy of a string, including null character, to the end +// of another string. Enough memory has to be available in the +// destination string. +// +// \param dst is a pointer onto the string where the other string +// will be appended. +// \param src is the string to append. +// \return the pointer string dst. +*/ +//---------------------------------------------------------------------- +char *n_strcat(char *dst, const char *src) +{ + int i,j,k; + i=(int)n_strlen(dst); + j=(int)n_strlen(src); + for(k=i;k<=j+i;k++) { + dst[k]=src[k-i]; + } + return dst; +} + + +//---------------------------------------------------------------------- +// n_toupper() +/*! Gives the upper-case letter corresponding to the lower-case +// letter passed as parameter. +// +// \param c is the ASCII code of the letter to transform. +// \return the corresponding upper-case letter +*/ +//---------------------------------------------------------------------- +int n_toupper(int c) +{ + if((c>='a')&&(c<='z')) + return c+('A'-'a'); + else return c; +} + +//---------------------------------------------------------------------- +// n_tolower() +/*! Gives the lower-case letter corresponding to the upper-case +// letter passed as parameter +// +// \param c is the ASCII code of the letter to transform. +// \return the corresponding lower-case letter +*/ +//---------------------------------------------------------------------- +int n_tolower(int c) +{ + if((c<='Z')&&(c>='A')) + return c+('a'-'A'); + else return c; +} + +//---------------------------------------------------------------------- +// n_atoi() +/*! String to integer conversion. +// +// \param c is a pointer onto a string. +// \return the corresponding value +*/ +//---------------------------------------------------------------------- +int n_atoi(const char *str) +{ + int i=0; + int fini=0; + int val=0; + int negative = 0; + if (str[i] == '-') { + negative = 1; i=1; + } + while(!fini) + { + if(str[i]==0 || str[i]<'0' || str[i]>'9') + fini=1; + else + { + val*=10; + val+=str[i]-'0'; + i++; + } + } + if (negative) return(-val); else return val; +} + +//---------------------------------------------------------------------- +// n_memcmp() +/*! Memory comparison. +// +// \param s1 is the first memory area, +// \param s2 is the second memory area. +// \param n size in bytes of the area to be compared. +// \return an integer less than, equal to, or greater than 0, +// according as s1 is lexicographically less than, equal to, +// or greater than s2 when taken to be unsigned characters. +// +*/ +//---------------------------------------------------------------------- +int n_memcmp(const void *s1, const void *s2, size_t n) +{ + unsigned char* c1=(unsigned char*)s1; + unsigned char* c2=(unsigned char*)s2; + + int comparaison=0; + int fini=0; + int i=0; + while ((!fini)&&(ic2[i]) { + fini=1; + comparaison=1; + } + i++; + } + return comparaison; +} + +//---------------------------------------------------------------------- +// n_memcpy() +/*! Memory copy. +// +// \param s1 is where the elements are to be copied, +// \param s2 is the memory area to copy. +// \param n size in bytes of the area to be copied. +// \return the memory area where the copy has been done. +*/ +//---------------------------------------------------------------------- +void *n_memcpy(void *s1, const void *s2, size_t n) +{ + + unsigned char* c1=(unsigned char*)s1; + unsigned char* c2=(unsigned char*)s2; + + int i=0; + if ((c1!=0)&&(c2!=0)) { + while(i> 4) & 0xf); + s[1] = TOHEX(addr[i] & 0xf); + s[2] = '\0'; + n_printf("%s ", s); + if ((((i+1)%16) == 0) || (i == len-1)) + n_printf("\n"); + } +} + +#define PUTCHAR(carac) \ + do { \ + if (result < len-1) *buff++ = carac;\ + result++; \ + } while (0) + + +//---------------------------------------------------------------------- +// n_vsnprintf() +/*! Build a string according to a specified format (internal function) +// +// Nachos vsnprintf accepts: +// %c to print a character, +// %s, to print a string, +// %d, to print an integer, +// %x, to print an integer in hexa +// %lx %ld same for 64-bit values +// %f, to print a floating point value +// +// \param buff the destination buffer to generate the string to +// \param len the size of buff, determines the number max of +// characters copied to buff (taking the final \0 into account) +// \param format the string to parse +// \param ap parameters to print +// +// \return the number of characters formatted (NOT including \0), +// that is, the number of characters that would have been written +// to the buffer if it were large enough. -1 on error. +*/ +//---------------------------------------------------------------------- +static int n_vsnprintf(char *buff, int len, const char *format, va_list ap) +{ + int i, result; + + if (!buff || !format || (len < 0)) { + return -1; + } + result = 0; + + for (i=0 ; format[i] != '\0' ; i++) { + switch (format[i]) { + case '%': + i++; + switch(format[i]) { + case '%': { + PUTCHAR('%'); + break; + } + case 'i': + case'd': { + int integer = (int) va_arg(ap,int); + int cpt2 = 0; + char buff_int[11]; + if (integer<0) {PUTCHAR('-'); + } + do { + int m10 = integer%10; + m10 = (m10 < 0)? -m10:m10; + buff_int[cpt2++]=(char)('0'+ m10); + integer=integer/10; + } while(integer!=0); + for (cpt2 = cpt2 - 1 ; cpt2 >= 0 ; cpt2--) { + PUTCHAR(buff_int[cpt2]); + } + break; + } + case 'l': { + i++; + switch(format[i]) { + case 'd': { + long longer = va_arg(ap,long); + int cpt2 = 0; + char buff_long[20]; + if (longer<0) { + PUTCHAR('-'); + } + do { + int m10 = longer%10; + m10 = (m10 < 0)? -m10:m10; + buff_long[cpt2++]=(char)('0'+ m10); + longer=longer/10; + } while(longer!=0); + for (cpt2 = cpt2 - 1 ; cpt2 >= 0 ; cpt2--) { + PUTCHAR(buff_long[cpt2]); + } + break; + } + case 'x': { + uint64_t hexa = va_arg(ap,long); + uint64_t nb; + uint32_t i, had_nonzero = 0; + for (i=0 ; i < 16 ; i++) { + nb = (hexa << (i*4)); + nb = (nb >> 60); + nb = nb & 0x000000000000000f; + // Skip the leading zeros + if (nb == 0) { + if (had_nonzero) { + PUTCHAR((uint8_t)'0'); + } + } + else { + had_nonzero = 1; + if (nb < 10) + PUTCHAR((uint8_t)'0'+(uint8_t)nb); + else + PUTCHAR((uint8_t)'a'+(uint8_t)(nb-10)); + } + } + if (! had_nonzero) + PUTCHAR((uint8_t)'0'); + break; + } + default: { + PUTCHAR('%'); + PUTCHAR('l'); + PUTCHAR(format[i]); + break; + } + } + + break; + } + case 'c': { + int value = va_arg(ap,int); + PUTCHAR((char)value); + break; + } + case 's': { + char *string = va_arg(ap,char *); + if (! string) + string = "(null)"; + for( ; *string != '\0' ; string++) + PUTCHAR(*string); + break; + } + case 'x': { + uint32_t hexa = va_arg(ap,int); + uint32_t nb; + uint32_t i, had_nonzero = 0; + for (i=0 ; i < 8 ; i++) { + nb = (hexa << (i*4)); + nb = (nb >> 28); + nb = nb & 0x0000000f; + // Skip the leading zeros + if (nb == 0) { + if (had_nonzero) + PUTCHAR((uint8_t)'0'); + } + else { + had_nonzero = 1; + if (nb < 10) + PUTCHAR((uint8_t)'0'+(uint8_t)nb); + else + PUTCHAR((uint8_t)'a'+(uint8_t)(nb-10)); + } + } + if (! had_nonzero) + PUTCHAR((uint8_t)'0'); + break; + } + /*case 'f': { + // Very simple routine to print floats as xxxx.yyyyy + // Not very good (unable to print large numbers) + // If anyone wants to re-write it, feel free ... + double f = (double) va_arg(ap,double); + int cpt2, j; + char buff_float[200]; + long ient,idec; + if (f<0) { + PUTCHAR('-'); + f = -f; + } + ient = (int)f; + // 100000 = print 5 digits max + idec = (int)((f - ((double)ient))*100000); + // Round up + if ( f - ((double)ient) - ((double)idec)/100000.0 >= 0.5E-5) + idec ++; + cpt2 = 0; + // Print digits after the '.' + for (j=0 ; j<5 ; j++) { + buff_float[cpt2++]=(char)('0'+(idec%10)); + idec=idec/10; + } + buff_float[cpt2++] = '.'; + // Print digits before the '.' + do { + buff_float[cpt2++]=(char)('0'+ (ient%10)); + ient=ient/10; + } while (ient!=0); + for(j = cpt2 - 1 ; j >= 0 ; j--) + PUTCHAR(buff_float[j]); + break; + } + */ + default: + PUTCHAR('%'); + PUTCHAR(format[i]); + } + break; + default: + PUTCHAR(format[i]); + } + } + *buff = '\0'; + return result; +} + +//---------------------------------------------------------------------- +// n_snprintf() +/*! Build a string according to a specified format +// +// Nachos snprintf accepts: +// %c to print a character, +// %s, to print a string, +// %d, to print an integer, +// %x, to print a string in hexa +// %f, to print a floating point value +// +// \param buff the destination buffer to generate the string to +// \param len the size of buff, determines the number max of +// characters copied to buff (taking the final \0 into account) +// \param format the string to parse +// \param ... the (variable number of) arguments +// +// \return the number of characters formatted (NOT including \0), +// that is, the number of characters that would have been written +// to the buffer if it were large enough. -1 on error. +*/ +//---------------------------------------------------------------------- +int n_snprintf(char * buff, int len, const char *format, ...){ + va_list ap; + va_start(ap, format); + len = n_vsnprintf(buff, len, format, ap); + va_end(ap); + return len; +} + +//---------------------------------------------------------------------- +// n_printf() +/*! Print to the standard output parameters. +// +// Nachos printf accepts: +// %c to print a character, +// %s, to print a string, +// %d, to print an integer, +// %x, to print a string in hexa +// %ld, %lx, same for 64-bit values +// %f, to print a floating point value +// +// \param parameters to print, +// \param type of print. +*/ +//---------------------------------------------------------------------- +void n_printf(const char *format, ...){ + + va_list ap; + char buff[200]; + int len; + + va_start(ap, format); + len = n_vsnprintf(buff, sizeof(buff), format, ap); + va_end(ap); + + if (len >= sizeof(buff)) { + len = sizeof(buff) - 1; + } + if (len > 0) { + Write(buff,len,CONSOLE_OUTPUT); + } +} + +//---------------------------------------------------------------------- +// n_read_int() +/*! +// Very basic minimalist read integer function, no error +// checking... +*/ +//---------------------------------------------------------------------- +int n_read_int(void) { + char buff[200]; + Read(buff,200,CONSOLE_INPUT); + return n_atoi(buff); +} diff --git a/test_programs/userlib/libnachos.h b/test_programs/userlib/libnachos.h new file mode 100644 index 0000000..f033ed5 --- /dev/null +++ b/test_programs/userlib/libnachos.h @@ -0,0 +1,87 @@ +/*! \file libnachos.h + \brief Function structures for programs + + Libnachos proposes several 'libc-like' functions + for: + Input-Output operations, + String operations, + Memory operations, + System calls are defined in kernel/syscalls.h + + Nachos-libc functions are prefixed by 'n' to avoid + any confusion with standard libc functions. + + * ----------------------------------------------------- + * This file is part of the Nachos-RiscV distribution + * Copyright (c) 2022 University of Rennes 1. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details + * (see see ). + * ----------------------------------------------------- +*/ + +#include "userlib/syscall.h" + +typedef void (*VoidNoArgFunctionPtr)(); +typedef unsigned int size_t; + +// Thread management +// ---------------------------- +ThreadId threadCreate(char * debug_name, VoidNoArgFunctionPtr func); + +// Input/Output operations : +// ------------------------------------ + +// Print on the standard output specified parameters. +void n_printf(const char *format, ...); + +// Format (of max length ) according to the format +int n_snprintf(char * buff, int len, const char *format, ...); + +// Read an integer on the standard input +int n_read_int(void); + +// String operations : +// ------------------- + +// Compare two strings byte by byte. +int n_strcmp(const char *s1, const char *s2); + +// Copy a string. +char* n_strcpy(char *dst, const char *src); + +// Return the number of bytes in a string. +size_t n_strlen(const char *s); + +// appends a copy of a string, to the end of another string. +char* n_strcat(char *dst, const char *src); + +// Return a upper-case letter, +// equivalent to the lower-case letter given. +int n_toupper(int c); + +// Return a lower-case letter, +// equivalent to the upper-case letter given. +int n_tolower(int c); + +// Convert a string in integer. +int n_atoi(const char *str); + +// Concerning memory area operations : +// ----------------------------------- + +// Compare two memory area, looking at the first n bytes . +int n_memcmp(const void *s1, const void *s2, size_t n); + +// Copy n byte from an memory area to another. +void* n_memcpy(void *s1, const void *s2, size_t n); + +// Set the first n bytes in a memory area to a specified value. +void* n_memset(void *s, int c, size_t n); diff --git a/test_programs/userlib/sys.s b/test_programs/userlib/sys.s new file mode 100644 index 0000000..64c3069 --- /dev/null +++ b/test_programs/userlib/sys.s @@ -0,0 +1,343 @@ +/* Start.s + * Assembly language assist for user programs running on top of Nachos. + * + * Since we don't want to pull in the entire C library, we define + * what we need for a user program here, namely Start and the system + * calls. + * + * ----------------------------------------------------- + * This file is part of the BurritOS distribution + * Copyright (c) 2022 University of Rennes 1. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details + * (see see ). + * ----------------------------------------------------- + */ + +#define IN_ASM +#include "userlib/syscall.h" + + // Equivalent to ".text", but with a different name, in order + // to be correctly handled by the ldscript + .section .sys,"ax",@progbits + + .align 2 + +/* ------------------------------------------------------------- + * __start + * Initialize running a C program, by calling "main". + * + * NOTE: This has to be first, so that it gets loaded at location 0. + * The Nachos kernel always starts a program by jumping to location 0. + * ------------------------------------------------------------- + */ + + .globl __start + .type __start, @function +__start: + +/* Call the program entry point */ + call main + li a0, 0 + call Exit + jr ra /* if we return from main, exit(0) */ + + +/* ------------------------------------------------------------- + * System call stubs: + * Assembly language assist to make system calls to the Nachos kernel. + * There is one stub per system call, that places the code for the + * system call into register r10, and leaves the arguments to the + * system call alone (in other words, arg1 is in r12, arg2 is + * in r13, arg3 is in r14, arg4 is in r15) + * + * The return value is in r10. This follows the standard C calling + * convention on the RISC-V. + * ------------------------------------------------------------- + */ + + .globl Halt + .type __Halt, @function +Halt: + addi a7,zero,SC_HALT + ecall + jr ra + + + .globl Exit + .type __Exit, @function +Exit: + addi a7,zero,SC_EXIT + ecall + jr ra + + + .globl Exec + .type __Exec, @function +Exec: + addi a7,zero,SC_EXEC + ecall + jr ra + + + .globl Join + .type __Join, @function +Join: + addi a7,zero,SC_JOIN + ecall + jr ra + + + .globl Create + .type __Create, @function +Create: + addi a7,zero,SC_CREATE + ecall + jr ra + + + .globl Open + .type __Open, @function +Open: + addi a7,zero,SC_OPEN + ecall + jr ra + + + .globl Read + .type __Read, @function +Read: + addi a7,zero,SC_READ + ecall + jr ra + + + + .globl Write + .type __Write, @function +Write: + addi a7,zero,SC_WRITE + ecall + jr ra + + + .globl Seek + .type __Seek, @function +Seek: + addi a7,zero,SC_SEEK + ecall + jr ra + + + .globl Close + .type __Close, @function +Close: + addi a7,zero,SC_CLOSE + ecall + jr ra + + + .globl FSList + .type __FSList, @function +FSList: + addi a7,zero,SC_FSLIST + ecall + jr ra + + + .globl newThread + .type __newThread, @function +newThread: + addi a7,zero,SC_NEW_THREAD + ecall + jr ra + + + .globl Remove + .type __Remove, @function +Remove: + addi a7,zero,SC_REMOVE + ecall + jr ra + + + .globl Yield + .type __Yield, @function +Yield: + addi a7,zero,SC_YIELD + ecall + jr ra + + + .globl PError + .type __PError, @function +PError: + addi a7,zero,SC_PERROR + ecall + jr ra + + + .globl P + .type __P, @function +P: + addi a7,zero,SC_P + ecall + jr ra + + + .globl V + .type __V, @function +V: + addi a7,zero,SC_V + ecall + jr ra + + .globl SemCreate + .type __SemCreate, @function +SemCreate: + addi a7,zero,SC_SEM_CREATE + ecall + jr ra + + + .globl SemDestroy + .type __SemDestroy, @function +SemDestroy: + addi a7,zero,SC_SEM_DESTROY + ecall + jr ra + + + .globl SysTime + .type __SysTime, @function +SysTime: + addi a7,zero,SC_SYS_TIME + ecall + jr ra + + + .globl LockCreate + .type __LockCreate, @function +LockCreate: + addi a7,zero,SC_LOCK_CREATE + ecall + jr ra + + .globl LockDestroy + .type __LockDestroy, @function +LockDestroy: + addi a7,zero,SC_LOCK_DESTROY + ecall + jr ra + + + .globl LockAcquire + .type __LockAquire, @function +LockAcquire: + addi a7,zero,SC_LOCK_ACQUIRE + ecall + jr ra + + + .globl LockRelease + .type __LockRelease, @function +LockRelease: + addi a7,zero,SC_LOCK_RELEASE + ecall + jr ra + + + .globl CondCreate + .type __CondCreate, @function +CondCreate: + addi a7,zero,SC_COND_CREATE + ecall + jr ra + + + .globl CondDestroy + .type __CondDestroy, @function +CondDestroy: + addi a7,zero,SC_COND_DESTROY + ecall + jr ra + + + .globl CondWait + .type __CondWait, @function +CondWait: + addi a7,zero,SC_COND_WAIT + ecall + jr ra + + + .globl CondSignal + .type __CondSignal, @function +CondSignal: + addi a7,zero,SC_COND_SIGNAL + ecall + jr ra + + + .globl CondBroadcast + .type __CondBroadcast, @function +CondBroadcast: + addi a7,zero,SC_COND_BROADCAST + ecall + jr ra + + + .globl TtySend + .type __TtySend, @function +TtySend: + addi a7,zero,SC_TTY_SEND + ecall + jr ra + + + .globl TtyReceive + .type __TtyReceive, @function +TtyReceive: + addi a7,zero,SC_TTY_RECEIVE + ecall + jr ra + + + .globl Mkdir + .type __Mkdir, @function +Mkdir: + addi a7,zero,SC_MKDIR + ecall + jr ra + + + .globl Rmdir + .type __Rmdir, @function +Rmdir: + addi a7,zero,SC_RMDIR + ecall + jr ra + + + .globl Mmap + .type __Mmap, @function +Mmap: + addi a7,zero,SC_MMAP + ecall + jr ra + + .globl Debug + .type __Debug, @function +Debug: + addi a7,zero,SC_DEBUG + ecall + jr ra + + diff --git a/test_programs/userlib/syscall.h b/test_programs/userlib/syscall.h new file mode 100644 index 0000000..e650db1 --- /dev/null +++ b/test_programs/userlib/syscall.h @@ -0,0 +1,287 @@ +/*! \file syscall.h + \brief Nachos system call interface. + + These are Nachos kernel operations + that can be invoked from user programs, by trapping to the kernel + via the "syscall" instruction. + + This file is included by user programs and by the Nachos kernel. + + Each of these is invoked by a user program by simply calling the + procedure; an assembly language stub stuffs the system call code + into a register, and traps to the kernel. The kernel procedures + are then invoked in the Nachos kernel, after appropriate error checking, + from the system call entry point in exception.cc. + + * ----------------------------------------------------- + * This file is part of the Nachos-RiscV distribution + * Copyright (c) 2022 University of Rennes 1. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details + * (see see ). + * ----------------------------------------------------- + */ + + +#ifndef SYSCALLS_H +#define SYSCALLS_H + +//#include "kernel/copyright.h" + +/* system call codes -- used by the stubs to tell the kernel which system call + * is being asked for + */ +#define SC_HALT 0 +#define SC_EXIT 1 +#define SC_EXEC 2 +#define SC_JOIN 3 +#define SC_CREATE 4 +#define SC_OPEN 5 +#define SC_READ 6 +#define SC_WRITE 7 +#define SC_SEEK 8 +#define SC_CLOSE 9 +#define SC_NEW_THREAD 10 +#define SC_YIELD 11 +#define SC_PERROR 12 +#define SC_P 13 +#define SC_V 14 +#define SC_SEM_CREATE 15 +#define SC_SEM_DESTROY 16 +#define SC_LOCK_CREATE 17 +#define SC_LOCK_DESTROY 18 +#define SC_LOCK_ACQUIRE 19 +#define SC_LOCK_RELEASE 20 +#define SC_COND_CREATE 21 +#define SC_COND_DESTROY 22 +#define SC_COND_WAIT 23 +#define SC_COND_SIGNAL 24 +#define SC_COND_BROADCAST 25 +#define SC_TTY_SEND 26 +#define SC_TTY_RECEIVE 27 +#define SC_MKDIR 28 +#define SC_RMDIR 29 +#define SC_REMOVE 30 +#define SC_FSLIST 31 +#define SC_SYS_TIME 32 +#define SC_MMAP 33 +#define SC_DEBUG 34 + +#ifndef IN_ASM + +/* The system call interface. These are the operations the Nachos + * kernel needs to support, to be able to run user programs. + * + */ + +typedef int t_error; + +/* Stop Nachos, and print out performance stats */ +void Halt(); + + +/* Return the time spent running Nachos */ + +/*! \brief Defines the Nachos basic time unit */ +typedef struct { + long seconds; + long nanos; +} Nachos_Time; +void SysTime(Nachos_Time *t); + +/* Address space control operations: Exit, Exec, and Join */ + +/* This user program is done (status = 0 means exited normally). */ +void Exit(int status); + +/* A unique identifier for a thread executed within a user program */ +typedef unsigned long ThreadId; + +/* Run the executable, stored in the Nachos file "name", and return the + * master thread identifier + */ +ThreadId Exec(char *name); + +/* Create a new thread in the current process + * Return thread identifier + */ +ThreadId newThread(char * debug_name, int func, int arg); + +/* Only return once the the thread "id" has finished. + */ +t_error Join(ThreadId id); + +/* Yield the CPU to another runnable thread, whether in this address space + * or not. + */ +void Yield(); + +/*! Print the last error message with the personalized one "mess" */ +void PError(char *mess); + +/* File system operations: Create, Open, Read, Write, Seek, Close + * These functions are patterned after UNIX -- files represent + * both files *and* hardware I/O devices. + * + * If this assignment is done before doing the file system assignment, + * note that the Nachos file system has a stub implementation, which + * will work for the purposes of testing out these routines. + */ + +/* A unique identifier for an open Nachos file. */ +typedef unsigned long OpenFileId; + +/* when an address space starts up, it has two open files, representing + * keyboard input and display output (in UNIX terms, stdin and stdout). + * Read and Write can be used directly on these, without first opening + * the console device. + */ +#define CONSOLE_INPUT 0 +#define CONSOLE_OUTPUT 1 + +/* Create a Nachos file, with "name" */ +t_error Create(char *name,int size); + +/* Open the Nachos file "name", and return an "OpenFileId" that can + * be used to read and write to the file. + */ +OpenFileId Open(char *name); + +/* Write "size" bytes from "buffer" to the open file. */ +t_error Write(char *buffer, int size, OpenFileId id); + +/* Read "size" bytes from the open file into "buffer". + * Return the number of bytes actually read -- if the open file isn't + * long enough, or if it is an I/O device, and there aren't enough + * characters to read, return whatever is available (for I/O devices, + * you should always wait until you can return at least one character). + */ +t_error Read(char *buffer, int size, OpenFileId id); + +/* Seek to a specified offset into an opened file */ +t_error Seek(int offset, OpenFileId id); + +#ifndef SYSDEP_H +/* Close the file, we're done reading and writing to it. */ +t_error Close(OpenFileId id); +#endif // SYSDEP_H + +/* Remove the file */ +t_error Remove(char* name); + +/******************************************************************/ +/* system calls concerning directory management */ + +/* Create a new repertory + Return a negative number if an error ocurred. +*/ +t_error Mkdir(char* name); + +/* Destroy a repertory, which must be empty. + Return a negative number if an error ocurred. +*/ +t_error Rmdir(char* name); + +/* List the content of NachOS FileSystem */ +t_error FSList(); + +/******************************************************************/ +/* User-level synchronization operations : */ + +/* System calls concerning semaphores management */ + +typedef unsigned long SemId; + +/* Create a semaphore, initialising it at count. + Return a Semid, which will enable to do operations on this + semaphore */ +SemId SemCreate(char * debug_name, int count); + +/* Destroy a semaphore identified by sema. + Return a negative number if an error occured during the destruction */ +t_error SemDestroy(SemId sema); + +/* Do the operation P() on the semaphore sema */ +t_error P(SemId sema); + +/* Do the operation V() on the semaphore sema */ +t_error V(SemId sema); + +/* System calls concerning locks management */ +typedef unsigned long LockId; + +/* Create a lock. + Return an identifier */ +LockId LockCreate(char * debug_name); + +/* Destroy a lock. + Return a negative number if an error ocurred + during the destruction. */ +t_error LockDestroy(LockId id); + +/* Do the operation Acquire on the lock id. + Return a negative number if an error ocurred. */ +t_error LockAcquire(LockId id); + +/* Do the operation Release on the lock id. + Return a negative number if an error ocurred. +*/ +t_error LockRelease(LockId id); + +/* System calls concerning conditions variables. */ +typedef unsigned long CondId; + +/* Create a new condition variable */ +CondId CondCreate(char * debug_name); + +/* Destroy a condition variable. + Return a negative number if an error ocurred. +*/ +t_error CondDestroy(CondId id); + +/* Do the operation Wait on a condition variable. + Returns a negative number if an error ocurred. +*/ +t_error CondWait(CondId cond); + +/* Do the operation Signal on a condition variable (wake up only one thread). + Return a negative number if an error ocurred. +*/ +t_error CondSignal(CondId cond); + +/* Do the operation Signal on a condition variable (wake up all threads). + Return a negative number if an error ocurred. +*/ +t_error CondBroadcast(CondId cond); + +/******************************************************************/ +/* System calls concerning serial port and console */ + +/* Send the message on the serial communication link. + Returns the number of bytes successfully sent. +*/ +int TtySend(char *mess); + +/* Wait for a message comming from the serial communication link. + The length of the buffer where the bytes will be copied is given as a parameter. + Returns the number of characters actually received. +*/ +int TtyReceive(char *mess,int length); + +/* Map an opened file in memory. Size is the size to be mapped in bytes. +*/ +void *Mmap(OpenFileId f, int size); + +/* For debug purpose +*/ +void Debug(int param); + +#endif // IN_ASM +#endif // SYSCALL_H From f1a03b96a32d09bfff0a3e3377a29c9d5a9a2dda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 13:01:36 +0100 Subject: [PATCH 111/128] Updated gitignore --- test_programs/.gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test_programs/.gitignore b/test_programs/.gitignore index 0a0178a..f7e49da 100644 --- a/test_programs/.gitignore +++ b/test_programs/.gitignore @@ -1,4 +1,4 @@ # Ignoring dump files *.dump *.o -./target \ No newline at end of file +target \ No newline at end of file From 765f5b83284087dfec2f7cb31bc749a71e90c529 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 13:02:03 +0100 Subject: [PATCH 112/128] Updated makefile --- test_programs/Makefile | 12 +++++- test_programs/Makefile.tests | 38 +++++++++++++++++++ test_programs/riscv_instructions/Makefile | 7 +++- .../riscv_instructions/boolean_logic/Makefile | 9 ++++- .../jump_instructions/Makefile | 6 ++- .../simple_arithmetics/Makefile | 6 ++- .../simple_arithmetics/unsigned_addition.c | 3 ++ 7 files changed, 72 insertions(+), 9 deletions(-) create mode 100644 test_programs/Makefile.tests diff --git a/test_programs/Makefile b/test_programs/Makefile index 662a888..ad2c039 100644 --- a/test_programs/Makefile +++ b/test_programs/Makefile @@ -6,8 +6,16 @@ include $(TOPDIR)/Makefile.config # dumps: $(MAKE) dumps -C riscv_instructions/ - mkdir -p ${TOPDIR}/target - find . -name '*.dump' -exec mv {} ${TOPDIR}/target \; + mkdir -p ${TOPDIR}/target/dumps/ + find . -name '*.dump' -exec mv {} ${TOPDIR}/target/dumps/ \; + +user_lib: + $(MAKE) -C userlib/ + +tests: user_lib + $(MAKE) tests -C riscv_instructions/ + mkdir -p ${TOPDIR}/target/guac/ + find . -name '*.guac' -exec mv {} ${TOPDIR}/target/guac/ \; clean: rm -rf $(TOPDIR)/target \ No newline at end of file diff --git a/test_programs/Makefile.tests b/test_programs/Makefile.tests new file mode 100644 index 0000000..681d31f --- /dev/null +++ b/test_programs/Makefile.tests @@ -0,0 +1,38 @@ +include $(TOPDIR)/Makefile.config +USERLIB = $(TOPDIR)/userlib +INCPATH += -I$(TOPDIR) -I$(USERLIB) +LDFLAGS = $(RISCV_LDFLAGS) -T $(USERLIB)/ldscript.lds +ASFLAGS = $(RISCV_ASFLAGS) $(INCPATH) +CFLAGS = $(RISCV_CFLAGS) $(INCPATH) + +# Rules +%.o: %.s + $(RISCV_AS) $(ASFLAGS) -c $< + +%.o: %.c + $(RISCV_GCC) $(CFLAGS) -c $< + +%.dump: %.o + $(RISCV_OBJCOPY) -j .text -O $(DUMP_FORMAT) $< $@ + +%.guac: %.o + $(RISCV_LD) $(LDFLAGS) $+ -o $@ + +# Dependencies +.%.d: %.s + @echo Generating dependencies for $< + @$(SHELL) -ec '$(GCC) -x assembler-with-cpp -M $(ASFLAGS) $< \ + | sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \ + [ -s $@ ] || rm -f $@' + +.%.d: %.c + @echo Generating dependencies for $< + @$(SHELL) -ec '$(GCC) -M $(CFLAGS) $< \ + | sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \ + [ -s $@ ] || rm -f $@' + +# Targets +#clean: +# rm -rf *.o 2> /dev/null +# rm -rf *.dump 2> /dev/null +# rm -rf *.guac 2> /dev/null \ No newline at end of file diff --git a/test_programs/riscv_instructions/Makefile b/test_programs/riscv_instructions/Makefile index c134d5f..22a1303 100644 --- a/test_programs/riscv_instructions/Makefile +++ b/test_programs/riscv_instructions/Makefile @@ -1,4 +1,9 @@ dumps: make dumps -C boolean_logic/ make dumps -C jump_instructions/ - make dumps -C simple_arithmetics/ \ No newline at end of file + make dumps -C simple_arithmetics/ + +tests: + make tests -C boolean_logic/ + make tests -C jump_instructions/ + make tests -C simple_arithmetics/ \ No newline at end of file diff --git a/test_programs/riscv_instructions/boolean_logic/Makefile b/test_programs/riscv_instructions/boolean_logic/Makefile index 2150f14..5f738e9 100644 --- a/test_programs/riscv_instructions/boolean_logic/Makefile +++ b/test_programs/riscv_instructions/boolean_logic/Makefile @@ -1,4 +1,9 @@ TOPDIR = ../.. -include $(TOPDIR)/Makefile.dumps +include $(TOPDIR)/Makefile.tests -dumps: comparisons.dump if.dump switch.dump \ No newline at end of file +dumps: comparisons.dump if.dump switch.dump + +tests: comparisons.guac if.guac switch.guac + +# Dependances +$(PROGRAMS): % : $(USERLIB)/sys.o $(USERLIB)/libnachos.o %.o \ No newline at end of file diff --git a/test_programs/riscv_instructions/jump_instructions/Makefile b/test_programs/riscv_instructions/jump_instructions/Makefile index 75b887b..ce69447 100644 --- a/test_programs/riscv_instructions/jump_instructions/Makefile +++ b/test_programs/riscv_instructions/jump_instructions/Makefile @@ -1,4 +1,6 @@ TOPDIR = ../.. -include $(TOPDIR)/Makefile.dumps +include $(TOPDIR)/Makefile.tests -dumps: jump.dump ret.dump \ No newline at end of file +dumps: jump.dump ret.dump + +tests: jump.guac ret.guac \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmetics/Makefile b/test_programs/riscv_instructions/simple_arithmetics/Makefile index d775b97..623b297 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/Makefile +++ b/test_programs/riscv_instructions/simple_arithmetics/Makefile @@ -1,4 +1,6 @@ TOPDIR = ../.. -include $(TOPDIR)/Makefile.dumps +include $(TOPDIR)/Makefile.tests -dumps: unsigned_addition.dump unsigned_division.dump unsigned_multiplication.dump unsigned_substraction.dump \ No newline at end of file +dumps: unsigned_addition.dump unsigned_division.dump unsigned_multiplication.dump unsigned_substraction.dump + +tests: unsigned_addition.guac unsigned_division.guac unsigned_multiplication.guac unsigned_substraction.guac \ No newline at end of file diff --git a/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c b/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c index 05a7829..f1c005a 100644 --- a/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c +++ b/test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.c @@ -1,3 +1,6 @@ +#include "userlib/syscall.h" +#include "userlib/libnachos.h" + // EXPECTS TWO VARIABLES WITH A VALUE OF UNSIGNED 1 int main() { unsigned int x = 0; From e60ca57bc75eb6cf3e94f51fd0e05c9d444af2cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 8 Mar 2023 13:04:03 +0100 Subject: [PATCH 113/128] Warning fix --- src/simulator/mem_cmp.rs | 47 ++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index febe371..7e7e8f5 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -1,5 +1,4 @@ use std::fs; -use std::io; use std::io::BufRead; use std::io::BufReader; use std::io::Lines; @@ -70,11 +69,11 @@ impl Section{ } } - Section{addr:addr, len:len, content:content} + Section{addr, len, content} } - fn print_Section(s: &Section){ + fn print_section(s: &Section){ println!("ADDR :: {:x}", s.addr); println!("LEN :: {:x}", s.len); println!("CONTENT :: {:?}", s.content); @@ -84,14 +83,14 @@ impl Section{ /* * Representation de l'etat de la mémoire (apres execution.... a confirmer), sous forme de sections */ -pub struct Mem_Checker{ +pub struct MemChecker{ pc: usize, sp: usize, sections: Vec
, } -impl Mem_Checker{ +impl MemChecker{ ///Translate lines of a file in e Vector of String ///We need this method to parse the memory we received @@ -104,7 +103,7 @@ impl Mem_Checker{ /// - A vector of String where each line of the file os an element of the vector fn vect_from_lines(lines: &mut Lines>, pc: &mut usize, sp: &mut usize) -> Vec{ let mut vector = Vec::new(); - for (i,line) in lines.enumerate() { + for (_,line) in lines.enumerate() { vector.push(line.unwrap()); } let size = vector.len(); @@ -121,16 +120,16 @@ impl Mem_Checker{ /// /// ### Return /// Mem-checker filled - pub fn from(path: &String) -> Mem_Checker { + pub fn from(path: &String) -> MemChecker { let file = fs::File::open(path).expect("Wrong filename"); - let reader = io::BufReader::new(file); + let reader = BufReader::new(file); let mut lines = reader.lines(); let mut pc: usize = 0; let mut sp: usize = 0; - let vector = Mem_Checker::vect_from_lines(&mut lines, &mut pc, &mut sp); + let vector = MemChecker::vect_from_lines(&mut lines, &mut pc, &mut sp); let mut sections: Vec
= Vec::new(); let mut tmp_addr_str: String = String::new(); @@ -159,7 +158,7 @@ impl Mem_Checker{ } - Mem_Checker{pc:pc, sp:sp, sections:sections} + MemChecker{pc, sp, sections} } @@ -168,13 +167,13 @@ impl Mem_Checker{ /// ### Parameter /// /// - **m_c** Contains the data we want to print - pub fn print_Mem_Checker(m_c: &Mem_Checker){ + pub fn print_mem_checker(m_c: &MemChecker){ println!("PC :: {:x}", m_c.pc); println!("SP :: {:x}", m_c.sp); for(i,s) in m_c.sections.iter().enumerate() { println!("\nSection {}\n", i); - Section::print_Section(&s); + Section::print_section(&s); } } @@ -185,7 +184,7 @@ impl Mem_Checker{ /// /// - **m_c** contains the data /// - **machine** contains the memry to fill - pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){ + pub fn fill_memory_from_mem_checker(m_c: &MemChecker, machine: &mut Machine){ machine.sp = m_c.sp; machine.int_reg.set_reg(2, m_c.pc as i64); @@ -204,9 +203,9 @@ impl Mem_Checker{ /* * FOR DEBUG */ - fn compare_print_m_c_machine(m_c: &Mem_Checker, machine: &mut Machine){ + fn compare_print_m_c_machine(m_c: &MemChecker, machine: &mut Machine){ - Mem_Checker::print_Mem_Checker(m_c); + MemChecker::print_mem_checker(m_c); for section in m_c.sections.iter() { @@ -222,7 +221,7 @@ impl Mem_Checker{ } - pub fn compare_machine_memory(m_c: &Mem_Checker, machine: &Machine) -> bool { + pub fn compare_machine_memory(m_c: &MemChecker, machine: &Machine) -> bool { for section in m_c.sections.iter() { for i in 0..section.len { @@ -252,7 +251,7 @@ fn string_hex_to_usize(s: &String) -> usize { for (i,c )in s.chars().enumerate(){ //println!("Current char :: {} :: Current pow :: {} ::", c, max_pow - (i as u32)); - let tmp: usize = (one_hex_to_dec(c) as usize); + let tmp: usize = one_hex_to_dec(c) as usize; ret_value += base.pow(max_pow - (i as u32))*tmp; } @@ -297,7 +296,7 @@ fn two_hex_to_u8(c1: char, c2: char) -> u8 { */ fn test_show_sections_file(){ let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); - let reader = io::BufReader::new(file); + let reader = BufReader::new(file); for line in reader.lines() { //println!("Tailles de la ligne : {}", @@ -318,14 +317,14 @@ mod tests { #[test] fn test_fill_memory(){ let path = "osef".to_string(); - let m_c = Mem_Checker::from(&path); + let m_c = MemChecker::from(&path); let mut machine = Machine::_init_machine(); - Mem_Checker::fill_memory_from_Mem_Checker(&m_c, &mut machine); + MemChecker::fill_memory_from_mem_checker(&m_c, &mut machine); print!("\n Comparing memory from loaded context\n\n"); - Mem_Checker::compare_print_m_c_machine(&m_c, &mut machine); + MemChecker::compare_print_m_c_machine(&m_c, &mut machine); } @@ -339,10 +338,10 @@ mod tests { } #[test] - fn test_create_Mem_Checker(){ + fn test_create_mem_checker(){ let path: String = "osef".to_string(); - let m_c = Mem_Checker::from(&path); - Mem_Checker::print_Mem_Checker(&m_c); + let m_c = MemChecker::from(&path); + MemChecker::print_mem_checker(&m_c); } From f37820ab5be7f402e5a445196b6c7473855031bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 13:04:13 +0100 Subject: [PATCH 114/128] Removed makefile.dumps --- test_programs/Makefile.dumps | 12 ------------ 1 file changed, 12 deletions(-) delete mode 100644 test_programs/Makefile.dumps diff --git a/test_programs/Makefile.dumps b/test_programs/Makefile.dumps deleted file mode 100644 index a9824c1..0000000 --- a/test_programs/Makefile.dumps +++ /dev/null @@ -1,12 +0,0 @@ -include $(TOPDIR)/Makefile.config - -%.o: %.c - $(RISCV_GCC) $(RISCV_CFLAGS) -c $< - - -%.dump: %.o - $(RISCV_OBJCOPY) -j .text -O $(DUMP_FORMAT) $< $@ - -clean: - rm -rf *.o 2> /dev/null - rm -rf *.dump 2> /dev/null \ No newline at end of file From 58890d85d1e524a99989698bfaf63bfc4811e57d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 13:05:59 +0100 Subject: [PATCH 115/128] Fixed naming conventions not followed --- src/main.rs | 4 ++-- src/simulator/mem_cmp.rs | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main.rs b/src/main.rs index 97c0ec1..64f37a3 100644 --- a/src/main.rs +++ b/src/main.rs @@ -6,8 +6,8 @@ use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); let path = "memoryJump.txt".to_string(); - let checker = mem_cmp::Mem_Checker::from(&path); - mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); + let checker = mem_cmp::MemChecker::from(&path); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); //Machine::print_memory(&mut m, 0x400000, 0x405000); //Machine::run(m); diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 7e7e8f5..cbc77fe 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -7,7 +7,6 @@ use crate::Machine; const MEM_SIZE : usize = 4096; - /* TRUCS MANQUANTS * Verifier qu'il y a un nombre pair de caractere hexa dans la ligne correspondante d'une section du fichier source * Sinon on ne peut pas automatiquement remplir chaque octect car 2 hexa = 1 octet From de0013ad3ee22e2cfd12c38cb673d8e998c36ea2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Rativel?= Date: Wed, 8 Mar 2023 13:34:12 +0100 Subject: [PATCH 116/128] remade compare_machine_memory --- src/simulator/mem_cmp.rs | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index cbc77fe..9c4d1da 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -220,17 +220,16 @@ impl MemChecker{ } + /// Compare sections of a memChecker and a machine memory + /// + /// ### Parameters + /// + /// - **m_c** contains section of the memory checker + /// - **machine** contains the main memory pub fn compare_machine_memory(m_c: &MemChecker, machine: &Machine) -> bool { - - for section in m_c.sections.iter() { - for i in 0..section.len { - if machine.main_memory[section.addr + i] != section.content[i] { - return false; - } - } - } - - return true; + m_c.sections.iter().map(|section| { + !(0..section.len).into_iter().all(|i| machine.main_memory[section.addr + i] == section.content[i]) + }).all(|e| e == true) } From 75734b9e913de44ad7d5db7ed673e97ac8fe915d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 12:42:20 +0000 Subject: [PATCH 117/128] Update .gitlab-ci.yml file --- .gitlab-ci.yml | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 .gitlab-ci.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 0000000..b954b98 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,45 @@ +# This file is a template, and might need editing before it works on your project. +# This is a sample GitLab CI/CD configuration file that should run without any modifications. +# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts, +# it uses echo commands to simulate the pipeline execution. +# +# A pipeline is composed of independent jobs that run scripts, grouped into stages. +# Stages run in sequential order, but jobs within stages run in parallel. +# +# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages +# +# You can copy and paste this template into a new `.gitlab-ci.yml` file. +# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword. +# +# To contribute improvements to CI/CD templates, please follow the Development guide at: +# https://docs.gitlab.com/ee/development/cicd/templates.html +# This specific template is located at: +# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml + +stages: # List of stages for jobs, and their order of execution + - build + - test + +build-job: # This job runs in the build stage, which runs first. + stage: build + image: rust:latest + script: + - echo "Compiling the code..." + - cargo build + - echo "Compile complete." + +unit-test-job: # This job runs in the test stage. + stage: test # It only starts when the job in the build stage completes successfully. + image: rust:latest + script: + - echo "Running unit tests..." + - cargo test + - echo "Code coverage is 90%" + +lint-test-job: # This job also runs in the test stage. + stage: test # It can run at the same time as unit-test-job (in parallel). + image: rust:latest + script: + - echo "Linting code... This will take about 10 seconds." + - cargo clippy + - echo "No lint issues found." \ No newline at end of file From 148664e2cdcbf29952de02b10ca816c9c8aa3ac9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 12:45:36 +0000 Subject: [PATCH 118/128] Update .gitlab-ci.yml file --- .gitlab-ci.yml | 34 ++++++++-------------------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b954b98..246ad21 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,44 +1,26 @@ -# This file is a template, and might need editing before it works on your project. -# This is a sample GitLab CI/CD configuration file that should run without any modifications. -# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts, -# it uses echo commands to simulate the pipeline execution. -# -# A pipeline is composed of independent jobs that run scripts, grouped into stages. -# Stages run in sequential order, but jobs within stages run in parallel. -# -# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages -# -# You can copy and paste this template into a new `.gitlab-ci.yml` file. -# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword. -# -# To contribute improvements to CI/CD templates, please follow the Development guide at: -# https://docs.gitlab.com/ee/development/cicd/templates.html -# This specific template is located at: -# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml +default: + image: rust:latest -stages: # List of stages for jobs, and their order of execution +stages: - build - test -build-job: # This job runs in the build stage, which runs first. +build-job: stage: build - image: rust:latest script: - echo "Compiling the code..." - cargo build - echo "Compile complete." -unit-test-job: # This job runs in the test stage. - stage: test # It only starts when the job in the build stage completes successfully. - image: rust:latest +unit-test-job: + stage: test script: - echo "Running unit tests..." - cargo test - echo "Code coverage is 90%" -lint-test-job: # This job also runs in the test stage. - stage: test # It can run at the same time as unit-test-job (in parallel). - image: rust:latest +lint-test-job: + stage: test script: - echo "Linting code... This will take about 10 seconds." - cargo clippy From 2cd7980cd035b5100148b55c075fb627a2f8344a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 12:51:31 +0000 Subject: [PATCH 119/128] Update .gitlab-ci.yml file --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 246ad21..7efbdeb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,5 +1,7 @@ default: image: rust:latest + before_script: + - curl https://sh.rustup.rs -sSf | sh -s -- --default-toolchain none stages: - build From 075d6cb7374b392d931e5c34cf8bcbd2b35e3a95 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 8 Mar 2023 17:58:38 +0100 Subject: [PATCH 120/128] add tests run programs --- src/main.rs | 4 +- src/simulator/machine.rs | 183 +++++++++++++++++++++++++++++++++++---- src/simulator/mem_cmp.rs | 8 +- 3 files changed, 172 insertions(+), 23 deletions(-) diff --git a/src/main.rs b/src/main.rs index 64f37a3..562ef00 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,10 +5,10 @@ use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); - let path = "memoryJump.txt".to_string(); + let path = "memoryComp.txt".to_string(); let checker = mem_cmp::MemChecker::from(&path); mem_cmp::MemChecker::fill_memory_from_mem_checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); //Machine::print_memory(&mut m, 0x400000, 0x405000); - //Machine::run(m); + Machine::run(&mut m); } diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 47ee672..55d13ab 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -68,7 +68,8 @@ pub struct Machine { pub int_reg : Register, pub fp_reg : Register, pub main_memory : Vec, - pub shiftmask : [u64 ; 64] + pub shiftmask : [u64 ; 64], + pub registers_trace : String // for tests // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -86,15 +87,18 @@ impl Machine { value >>= 1; } - Machine { + let mut ret = Machine { pc : 0, sp: 0, int_reg : Register::::init(), fp_reg : Register::::init(), main_memory : vec![0; MEM_SIZE], - shiftmask - } - + shiftmask, + registers_trace : String::from("") + }; + + ret.int_reg.set_reg(10, -1); + ret } /// Read from main memory of the machine @@ -153,12 +157,10 @@ impl Machine { pub fn print_machine_status(machine: &mut Machine) { println!("######### Machine status #########"); for i in (0..32).step_by(3) { - print!(">{0: <4} : {1:<8x}", print::REG_X[i], machine.int_reg.get_reg(i)); - print!("\t"); - print!(">{0: <4} : {1:<8x}", print::REG_X[i+1], machine.int_reg.get_reg(i+1)); - print!("\t"); + print!(">{0: <4} : {1:<16x} ", print::REG_X[i], machine.int_reg.get_reg(i)); + print!(">{0: <4} : {1:<16x} ", print::REG_X[i+1], machine.int_reg.get_reg(i+1)); if i+2 < 32 { - print!(">{0: <4} : {1:<8x}", print::REG_X[i+2], machine.int_reg.get_reg(i+2)); + print!(">{0: <4} : {1:<16x} ", print::REG_X[i+2], machine.int_reg.get_reg(i+2)); } println!(); } @@ -170,14 +172,22 @@ impl Machine { println!("##################################"); } + pub fn string_registers(machine: &mut Machine) -> String { + let mut s = String::from(""); + for i in 0..32 { + s.push_str(format!("{} ", machine.int_reg.get_reg(i)).as_str()); + } + s + } + /// Execute the instructions table of a machine putted in param /// /// ### Parameters /// /// - **machine** which contains a table of instructions - pub fn run(machine : Machine){ - let mut m = machine; - while Machine::one_instruction(&mut m) == 0 {} + pub fn run(machine : &mut Machine){ + while Machine::one_instruction(machine) == 0 {} + println!("trace : \n{}", machine.registers_trace); } /// execute the current instruction @@ -212,8 +222,10 @@ impl Machine { Self::print_machine_status(machine); println!("executing instruction : {:016x} at pc {:x}", val, machine.pc); println!("{}", print::print(decode(val), machine.pc as i32)); + let trace = Self::string_registers(machine); + machine.registers_trace.push_str(format!("{}\n", trace).as_str()); - + machine.pc += 4; match inst.opcode { RISCV_LUI => { @@ -633,7 +645,6 @@ impl Machine { _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, } - machine.pc += 4; return 0; } @@ -654,8 +665,10 @@ impl Machine { } #[cfg(test)] - mod test { - use crate::simulator::machine::Machine; +mod test { + use std::fs; + + use crate::simulator::{machine::Machine, mem_cmp}; #[test] fn test_read_memory() { @@ -677,4 +690,140 @@ impl Machine { assert_eq!(43, m.main_memory[10]); assert_eq!(150, m.main_memory[11]); } + + #[test] + fn test_comp() { + let mut m = Machine::_init_machine(); + let path_before = "memoryComp.txt".to_string(); + let path_after = "memoryCompEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryCompTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_div() { + let mut m = Machine::_init_machine(); + let path_before = "memoryDiv.txt".to_string(); + let path_after = "memoryDivEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryDivTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_if() { + let mut m = Machine::_init_machine(); + let path_before = "memoryIf.txt".to_string(); + let path_after = "memoryIfEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryIfTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_jump() { + let mut m = Machine::_init_machine(); + let path_before = "memoryJump.txt".to_string(); + let path_after = "memoryJumpEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryJumpTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_mul() { + let mut m = Machine::_init_machine(); + let path_before = "memoryMul.txt".to_string(); + let path_after = "memoryMulEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryMulTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_ret() { + let mut m = Machine::_init_machine(); + let path_before = "memoryRet.txt".to_string(); + let path_after = "memoryRetEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memoryRetTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_sub() { + let mut m = Machine::_init_machine(); + let path_before = "memorySub.txt".to_string(); + let path_after = "memorySubEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memorySubTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } + + #[test] + fn test_switch() { + let mut m = Machine::_init_machine(); + let path_before = "memorySwitch.txt".to_string(); + let path_after = "memorySwitchEnd.txt".to_string(); + let memory_before = mem_cmp::MemChecker::from(&path_before); + let memory_after = mem_cmp::MemChecker::from(&path_after); + mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m); + Machine::run(&mut m); + + let path_trace = "memorySwitchTrace.txt".to_string(); + let expected_trace = fs::read_to_string(path_trace).unwrap(); + + assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m)); + assert!(expected_trace.contains(m.registers_trace.as_str())); + } } diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 9c4d1da..70f86f5 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -2,6 +2,7 @@ use std::fs; use std::io::BufRead; use std::io::BufReader; use std::io::Lines; +use std::io::Read; use crate::Machine; const MEM_SIZE : usize = 4096; @@ -186,7 +187,7 @@ impl MemChecker{ pub fn fill_memory_from_mem_checker(m_c: &MemChecker, machine: &mut Machine){ machine.sp = m_c.sp; - machine.int_reg.set_reg(2, m_c.pc as i64); + machine.int_reg.set_reg(2, m_c.sp as i64); machine.pc = m_c.pc as u64; @@ -228,11 +229,10 @@ impl MemChecker{ /// - **machine** contains the main memory pub fn compare_machine_memory(m_c: &MemChecker, machine: &Machine) -> bool { m_c.sections.iter().map(|section| { - !(0..section.len).into_iter().all(|i| machine.main_memory[section.addr + i] == section.content[i]) - }).all(|e| e == true) + (0..section.len).into_iter().all(|i| machine.main_memory[section.addr + i] == section.content[i]) + }).all(|e| e) } - } From 187614d49ea097d457842428f6396727ba0bc3cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 8 Mar 2023 17:15:49 +0000 Subject: [PATCH 121/128] Update .gitlab-ci.yml file --- .gitlab-ci.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7efbdeb..246ad21 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,5 @@ default: image: rust:latest - before_script: - - curl https://sh.rustup.rs -sSf | sh -s -- --default-toolchain none stages: - build From 5155b62b06808b4335e372e51755513efc5ed30a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 10:32:20 +0100 Subject: [PATCH 122/128] Added proper error handling to extract_memory_method --- src/simulator/machine.rs | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 55d13ab..48ff028 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -150,8 +150,16 @@ impl Machine { /// /// - **machine** contains the memory pub fn extract_memory(machine: &mut Machine){ - let mut file = File::create("burritos_memory.txt").unwrap(); - file.write(&machine.main_memory); + let file_path = "burritos_memory.txt"; + let write_to_file = |path| -> std::io::Result { + let mut file = File::create(path)?; + file.write_all(&machine.main_memory)?; + Ok(file) + }; + match write_to_file(file_path) { + Err(e) => eprintln!("Failed to write memory to file: {}", e), + Ok(_) => println!("Memory extracted to {}", file_path) + }; } pub fn print_machine_status(machine: &mut Machine) { From 6db52669b492826f36ec13de23f31dd42a4d0fad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 10:34:13 +0100 Subject: [PATCH 123/128] Removed useless variable --- src/simulator/print.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 60a2936..54bcddf 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -139,7 +139,6 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("fnmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3]) }, RISCV_FP => { - let name: &str; match ins.funct7 { RISCV_FP_ADD => { format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2]) From 44e3f586e2657dac6c272446c3497267345f3798 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 10:38:58 +0100 Subject: [PATCH 124/128] Fixed some clippy complaining --- src/simulator/mem_cmp.rs | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 70f86f5..00c45b8 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -2,7 +2,6 @@ use std::fs; use std::io::BufRead; use std::io::BufReader; use std::io::Lines; -use std::io::Read; use crate::Machine; const MEM_SIZE : usize = 4096; @@ -239,7 +238,7 @@ impl MemChecker{ fn string_hex_to_usize(s: &String) -> usize { - if s.len() == 0 { + if s.is_empty() { return 0; } @@ -253,7 +252,7 @@ fn string_hex_to_usize(s: &String) -> usize { ret_value += base.pow(max_pow - (i as u32))*tmp; } - return ret_value; + ret_value } @@ -271,8 +270,7 @@ fn one_hex_to_dec(c: char) -> u8 { 'E' | 'e' => 14, 'F' | 'f' => 15, _ => { - let ret : u8 = c.to_digit(10).unwrap() as u8; - return ret; + c.to_digit(10).unwrap() as u8 }, } } @@ -368,12 +366,7 @@ mod tests { }; let section = Section::from(§ion_format); - let mut expected_vec: Vec = Vec::new(); - expected_vec.push(0u8); - expected_vec.push(255u8); - expected_vec.push(10u8); - expected_vec.push(160u8); - expected_vec.push(165u8); + let expected_vec: Vec = vec![0u8, 255u8, 10u8, 160u8, 165u8]; //println!("Vec from created section {:?}", §ion.content); //println!("Expected vec {:?}", &expected_vec); @@ -384,13 +377,13 @@ mod tests { #[test] fn test_mod(){ let cond = (0%2) == 0; - assert_eq!(true, cond); + assert!(cond); } #[test] fn test_mod_2(){ let cond = (1%2) == 1; - assert_eq!(true, cond); + assert!(cond); } #[test] From be8435cf834780cc2d226b3122fcd28c95102e1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 10:59:14 +0100 Subject: [PATCH 125/128] Cleaned clippy lint warnings from machine.rs --- src/simulator/machine.rs | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 48ff028..9aeadef 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -149,7 +149,7 @@ impl Machine { /// ### Parameters /// /// - **machine** contains the memory - pub fn extract_memory(machine: &mut Machine){ + pub fn _extract_memory(machine: &mut Machine){ let file_path = "burritos_memory.txt"; let write_to_file = |path| -> std::io::Result { let mut file = File::create(path)?; @@ -221,8 +221,8 @@ impl Machine { panic!("ERROR : number max of instructions rushed"); } let mut val: [u8; 4] = [0; 4]; - for i in 0..4 { - val[i] = machine.main_memory[machine.pc as usize + i]; + for (i, mut _item) in val.iter_mut().enumerate() { + _item = &mut machine.main_memory[machine.pc as usize + i]; } let val = u32::from_be_bytes(val) as u64; @@ -345,7 +345,7 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64); }, RISCV_OPI_SLTI => { - machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } ); + machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64) as i64); }, RISCV_OPI_XORI => { machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64); @@ -465,12 +465,11 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, result); }, RISCV_OPIW_SRW => { - let result; - if inst.funct7 == RISCV_OPIW_SRW_SRLIW { - result = (local_data >> inst.shamt) & machine.shiftmask[32 + inst.shamt as usize] as i64; + let result = if inst.funct7 == RISCV_OPIW_SRW_SRLIW { + (local_data >> inst.shamt) & machine.shiftmask[32 + inst.shamt as usize] as i64 } else { // SRAIW - result = local_data >> inst.shamt; - } + local_data >> inst.shamt + }; machine.int_reg.set_reg(inst.rd as usize, result); }, _ => { @@ -627,13 +626,13 @@ impl Machine { RISCV_FP_FCMP => { match inst.funct3 { RISCV_FP_FCMP_FEQ => { - machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); + machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize)) as i64); }, RISCV_FP_FCMP_FLT => { - machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); + machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize)) as i64); }, RISCV_FP_FCMP_FLE => { - machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0}); + machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize)) as i64); }, _ => { panic!("this instruction ({}) doesn't exists", inst.value); @@ -653,14 +652,14 @@ impl Machine { _ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)}, } - return 0; + 0 } /// print memory FOR DEBUG /// /// "@"adresse [16 bytes] - pub fn print_memory(machine : &mut Machine, from: usize, to: usize) { + pub fn _print_memory(machine : &mut Machine, from: usize, to: usize) { for i in from..to { if i%16 == 0 { print!("\n@{:04x} ", i); From 6ee74ba1264264bb6bc045e65fd6e86b737d09a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 11:03:54 +0100 Subject: [PATCH 126/128] Fixed more clippy complaining --- src/simulator/loader.rs | 2 +- src/simulator/mem_cmp.rs | 20 +++----------------- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs index 7d31d18..b7b4b36 100644 --- a/src/simulator/loader.rs +++ b/src/simulator/loader.rs @@ -15,7 +15,7 @@ use std::io::BufRead; /// /// - **path** the path of the file to load /// - **size** the number of bytes to write (1, 2, 4 or 8) -pub fn load(path : &str, instruction_size: i32) -> Machine { +pub fn _load(path : &str, instruction_size: i32) -> Machine { let file = fs::File::open(path).expect("Wrong filename"); let reader = io::BufReader::new(file); let mut machine = Machine::_init_machine(); diff --git a/src/simulator/mem_cmp.rs b/src/simulator/mem_cmp.rs index 00c45b8..780437e 100644 --- a/src/simulator/mem_cmp.rs +++ b/src/simulator/mem_cmp.rs @@ -55,7 +55,6 @@ impl Section{ let len: usize = string_hex_to_usize(§ion.len); let mut tmp_a: char = ' '; - let mut tmp_b: char = ' '; for (i, c) in section.content.chars().enumerate(){ @@ -63,8 +62,7 @@ impl Section{ tmp_a = c; } else { - tmp_b = c; - content.push(two_hex_to_u8(tmp_a,tmp_b)); + content.push(two_hex_to_u8(tmp_a,c)); } } @@ -150,7 +148,7 @@ impl MemChecker{ let section_f = SectionFormat{ addr: tmp_addr_str.clone(), len: tmp_len_str.clone(), - content: current_line.clone().replace(" ", ""), + content: current_line.clone().replace(' ', ""), }; sections.push(Section::from(§ion_f)); } @@ -172,7 +170,7 @@ impl MemChecker{ for(i,s) in m_c.sections.iter().enumerate() { println!("\nSection {}\n", i); - Section::print_section(&s); + Section::print_section(s); } } @@ -374,18 +372,6 @@ mod tests { assert_eq!(section.content, expected_vec); } - #[test] - fn test_mod(){ - let cond = (0%2) == 0; - assert!(cond); - } - - #[test] - fn test_mod_2(){ - let cond = (1%2) == 1; - assert!(cond); - } - #[test] fn test_hex_1(){ let b = two_hex_to_u8('0', '0'); From 1081c910ee31ad2e7d3434c20365270851f8c7f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 11:12:49 +0100 Subject: [PATCH 127/128] Updated CI --- .gitlab-ci.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 246ad21..6559645 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -17,11 +17,11 @@ unit-test-job: script: - echo "Running unit tests..." - cargo test - - echo "Code coverage is 90%" lint-test-job: + only: + - merge_requests stage: test script: - - echo "Linting code... This will take about 10 seconds." - - cargo clippy - - echo "No lint issues found." \ No newline at end of file + - echo "Linting code..." + - cargo clippy \ No newline at end of file From a61f4bcc1de1dcb909d7b7ee72e6221394d151ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 10 Mar 2023 16:22:44 +0100 Subject: [PATCH 128/128] Repo clean-up --- .gitignore | 3 +- file.txt | 483 ------------------------------------------ memory.txt | 8 - memoryComp.txt | 8 - memoryDiv.txt | 8 - memoryIf.txt | 8 - memoryJump.txt | 8 - memoryMul.txt | 8 - memoryRet.txt | 8 - memorySub.txt | 8 - memorySwitch.txt | 8 - old_section.txt | 17 -- test_file_section.txt | 2 - 13 files changed, 2 insertions(+), 575 deletions(-) delete mode 100644 file.txt delete mode 100644 memory.txt delete mode 100644 memoryComp.txt delete mode 100644 memoryDiv.txt delete mode 100644 memoryIf.txt delete mode 100644 memoryJump.txt delete mode 100644 memoryMul.txt delete mode 100644 memoryRet.txt delete mode 100644 memorySub.txt delete mode 100644 memorySwitch.txt delete mode 100644 old_section.txt delete mode 100644 test_file_section.txt diff --git a/.gitignore b/.gitignore index d114b83..da74d9f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ /target /.idea -*.iml \ No newline at end of file +*.iml +*.txt \ No newline at end of file diff --git a/file.txt b/file.txt deleted file mode 100644 index 5caa50c..0000000 --- a/file.txt +++ /dev/null @@ -1,483 +0,0 @@ - -./test_programs/riscv_instructions/simple_arithmetics/unsigned_addition.o: file format elf64-littleriscv - - -Disassembly of section .text: - -00000000000100e8 : - 100e8: ff010113 addi sp,sp,-16 - 100ec: 00000593 li a1,0 - 100f0: 00813023 sd s0,0(sp) - 100f4: 00113423 sd ra,8(sp) - 100f8: 00050413 mv s0,a0 - 100fc: 29c000ef jal ra,10398 <__call_exitprocs> - 10100: f481b503 ld a0,-184(gp) # 11d78 <_global_impure_ptr> - 10104: 05853783 ld a5,88(a0) - 10108: 00078463 beqz a5,10110 - 1010c: 000780e7 jalr a5 - 10110: 00040513 mv a0,s0 - 10114: 4c4000ef jal ra,105d8 <_exit> - -0000000000010118 : - 10118: 00000793 li a5,0 - 1011c: 00078863 beqz a5,1012c - 10120: 00010537 lui a0,0x10 - 10124: 4c050513 addi a0,a0,1216 # 104c0 <__libc_fini_array> - 10128: 3f40006f j 1051c - 1012c: 00008067 ret - -0000000000010130 <_start>: - 10130: 00002197 auipc gp,0x2 - 10134: d0018193 addi gp,gp,-768 # 11e30 <__global_pointer$> - 10138: f6018513 addi a0,gp,-160 # 11d90 - 1013c: f9818613 addi a2,gp,-104 # 11dc8 <__BSS_END__> - 10140: 40a60633 sub a2,a2,a0 - 10144: 00000593 li a1,0 - 10148: 174000ef jal ra,102bc - 1014c: 00000517 auipc a0,0x0 - 10150: 3d050513 addi a0,a0,976 # 1051c - 10154: 00050863 beqz a0,10164 <_start+0x34> - 10158: 00000517 auipc a0,0x0 - 1015c: 36850513 addi a0,a0,872 # 104c0 <__libc_fini_array> - 10160: 3bc000ef jal ra,1051c - 10164: 0bc000ef jal ra,10220 <__libc_init_array> - 10168: 00012503 lw a0,0(sp) - 1016c: 00810593 addi a1,sp,8 - 10170: 00000613 li a2,0 - 10174: 06c000ef jal ra,101e0
- 10178: f71ff06f j 100e8 - -000000000001017c <__do_global_dtors_aux>: - 1017c: ff010113 addi sp,sp,-16 - 10180: 00813023 sd s0,0(sp) - 10184: f601c783 lbu a5,-160(gp) # 11d90 - 10188: 00113423 sd ra,8(sp) - 1018c: 02079263 bnez a5,101b0 <__do_global_dtors_aux+0x34> - 10190: 00000793 li a5,0 - 10194: 00078a63 beqz a5,101a8 <__do_global_dtors_aux+0x2c> - 10198: 00011537 lui a0,0x11 - 1019c: 61050513 addi a0,a0,1552 # 11610 <__FRAME_END__> - 101a0: 00000097 auipc ra,0x0 - 101a4: 000000e7 jalr zero # 0 - 101a8: 00100793 li a5,1 - 101ac: f6f18023 sb a5,-160(gp) # 11d90 - 101b0: 00813083 ld ra,8(sp) - 101b4: 00013403 ld s0,0(sp) - 101b8: 01010113 addi sp,sp,16 - 101bc: 00008067 ret - -00000000000101c0 : - 101c0: 00000793 li a5,0 - 101c4: 00078c63 beqz a5,101dc - 101c8: 00011537 lui a0,0x11 - 101cc: f6818593 addi a1,gp,-152 # 11d98 - 101d0: 61050513 addi a0,a0,1552 # 11610 <__FRAME_END__> - 101d4: 00000317 auipc t1,0x0 - 101d8: 00000067 jr zero # 0 - 101dc: 00008067 ret - -00000000000101e0
: - 101e0: fe010113 addi sp,sp,-32 - 101e4: 00813c23 sd s0,24(sp) - 101e8: 02010413 addi s0,sp,32 - 101ec: fe042623 sw zero,-20(s0) - 101f0: 00100793 li a5,1 - 101f4: fef42423 sw a5,-24(s0) - 101f8: fec42783 lw a5,-20(s0) - 101fc: 00078713 mv a4,a5 - 10200: fe842783 lw a5,-24(s0) - 10204: 00f707bb addw a5,a4,a5 - 10208: fef42623 sw a5,-20(s0) - 1020c: 00000793 li a5,0 - 10210: 00078513 mv a0,a5 - 10214: 01813403 ld s0,24(sp) - 10218: 02010113 addi sp,sp,32 - 1021c: 00008067 ret - -0000000000010220 <__libc_init_array>: - 10220: fe010113 addi sp,sp,-32 - 10224: 00813823 sd s0,16(sp) - 10228: 000117b7 lui a5,0x11 - 1022c: 00011437 lui s0,0x11 - 10230: 01213023 sd s2,0(sp) - 10234: 61478793 addi a5,a5,1556 # 11614 <__preinit_array_end> - 10238: 61440713 addi a4,s0,1556 # 11614 <__preinit_array_end> - 1023c: 00113c23 sd ra,24(sp) - 10240: 00913423 sd s1,8(sp) - 10244: 40e78933 sub s2,a5,a4 - 10248: 02e78263 beq a5,a4,1026c <__libc_init_array+0x4c> - 1024c: 40395913 srai s2,s2,0x3 - 10250: 61440413 addi s0,s0,1556 - 10254: 00000493 li s1,0 - 10258: 00043783 ld a5,0(s0) - 1025c: 00148493 addi s1,s1,1 - 10260: 00840413 addi s0,s0,8 - 10264: 000780e7 jalr a5 - 10268: ff24e8e3 bltu s1,s2,10258 <__libc_init_array+0x38> - 1026c: 00011437 lui s0,0x11 - 10270: 000117b7 lui a5,0x11 - 10274: 62878793 addi a5,a5,1576 # 11628 <__do_global_dtors_aux_fini_array_entry> - 10278: 61840713 addi a4,s0,1560 # 11618 <__init_array_start> - 1027c: 40e78933 sub s2,a5,a4 - 10280: 40395913 srai s2,s2,0x3 - 10284: 02e78063 beq a5,a4,102a4 <__libc_init_array+0x84> - 10288: 61840413 addi s0,s0,1560 - 1028c: 00000493 li s1,0 - 10290: 00043783 ld a5,0(s0) - 10294: 00148493 addi s1,s1,1 - 10298: 00840413 addi s0,s0,8 - 1029c: 000780e7 jalr a5 - 102a0: ff24e8e3 bltu s1,s2,10290 <__libc_init_array+0x70> - 102a4: 01813083 ld ra,24(sp) - 102a8: 01013403 ld s0,16(sp) - 102ac: 00813483 ld s1,8(sp) - 102b0: 00013903 ld s2,0(sp) - 102b4: 02010113 addi sp,sp,32 - 102b8: 00008067 ret - -00000000000102bc : - 102bc: 00f00313 li t1,15 - 102c0: 00050713 mv a4,a0 - 102c4: 02c37a63 bgeu t1,a2,102f8 - 102c8: 00f77793 andi a5,a4,15 - 102cc: 0a079063 bnez a5,1036c - 102d0: 06059e63 bnez a1,1034c - 102d4: ff067693 andi a3,a2,-16 - 102d8: 00f67613 andi a2,a2,15 - 102dc: 00e686b3 add a3,a3,a4 - 102e0: 00b73023 sd a1,0(a4) - 102e4: 00b73423 sd a1,8(a4) - 102e8: 01070713 addi a4,a4,16 - 102ec: fed76ae3 bltu a4,a3,102e0 - 102f0: 00061463 bnez a2,102f8 - 102f4: 00008067 ret - 102f8: 40c306b3 sub a3,t1,a2 - 102fc: 00269693 slli a3,a3,0x2 - 10300: 00000297 auipc t0,0x0 - 10304: 005686b3 add a3,a3,t0 - 10308: 00c68067 jr 12(a3) - 1030c: 00b70723 sb a1,14(a4) - 10310: 00b706a3 sb a1,13(a4) - 10314: 00b70623 sb a1,12(a4) - 10318: 00b705a3 sb a1,11(a4) - 1031c: 00b70523 sb a1,10(a4) - 10320: 00b704a3 sb a1,9(a4) - 10324: 00b70423 sb a1,8(a4) - 10328: 00b703a3 sb a1,7(a4) - 1032c: 00b70323 sb a1,6(a4) - 10330: 00b702a3 sb a1,5(a4) - 10334: 00b70223 sb a1,4(a4) - 10338: 00b701a3 sb a1,3(a4) - 1033c: 00b70123 sb a1,2(a4) - 10340: 00b700a3 sb a1,1(a4) - 10344: 00b70023 sb a1,0(a4) - 10348: 00008067 ret - 1034c: 0ff5f593 zext.b a1,a1 - 10350: 00859693 slli a3,a1,0x8 - 10354: 00d5e5b3 or a1,a1,a3 - 10358: 01059693 slli a3,a1,0x10 - 1035c: 00d5e5b3 or a1,a1,a3 - 10360: 02059693 slli a3,a1,0x20 - 10364: 00d5e5b3 or a1,a1,a3 - 10368: f6dff06f j 102d4 - 1036c: 00279693 slli a3,a5,0x2 - 10370: 00000297 auipc t0,0x0 - 10374: 005686b3 add a3,a3,t0 - 10378: 00008293 mv t0,ra - 1037c: f98680e7 jalr -104(a3) - 10380: 00028093 mv ra,t0 - 10384: ff078793 addi a5,a5,-16 - 10388: 40f70733 sub a4,a4,a5 - 1038c: 00f60633 add a2,a2,a5 - 10390: f6c374e3 bgeu t1,a2,102f8 - 10394: f3dff06f j 102d0 - -0000000000010398 <__call_exitprocs>: - 10398: fb010113 addi sp,sp,-80 - 1039c: 03413023 sd s4,32(sp) - 103a0: f481ba03 ld s4,-184(gp) # 11d78 <_global_impure_ptr> - 103a4: 03213823 sd s2,48(sp) - 103a8: 04113423 sd ra,72(sp) - 103ac: 1f8a3903 ld s2,504(s4) - 103b0: 04813023 sd s0,64(sp) - 103b4: 02913c23 sd s1,56(sp) - 103b8: 03313423 sd s3,40(sp) - 103bc: 01513c23 sd s5,24(sp) - 103c0: 01613823 sd s6,16(sp) - 103c4: 01713423 sd s7,8(sp) - 103c8: 01813023 sd s8,0(sp) - 103cc: 04090063 beqz s2,1040c <__call_exitprocs+0x74> - 103d0: 00050b13 mv s6,a0 - 103d4: 00058b93 mv s7,a1 - 103d8: 00100a93 li s5,1 - 103dc: fff00993 li s3,-1 - 103e0: 00892483 lw s1,8(s2) - 103e4: fff4841b addiw s0,s1,-1 - 103e8: 02044263 bltz s0,1040c <__call_exitprocs+0x74> - 103ec: 00349493 slli s1,s1,0x3 - 103f0: 009904b3 add s1,s2,s1 - 103f4: 040b8463 beqz s7,1043c <__call_exitprocs+0xa4> - 103f8: 2084b783 ld a5,520(s1) - 103fc: 05778063 beq a5,s7,1043c <__call_exitprocs+0xa4> - 10400: fff4041b addiw s0,s0,-1 - 10404: ff848493 addi s1,s1,-8 - 10408: ff3416e3 bne s0,s3,103f4 <__call_exitprocs+0x5c> - 1040c: 04813083 ld ra,72(sp) - 10410: 04013403 ld s0,64(sp) - 10414: 03813483 ld s1,56(sp) - 10418: 03013903 ld s2,48(sp) - 1041c: 02813983 ld s3,40(sp) - 10420: 02013a03 ld s4,32(sp) - 10424: 01813a83 ld s5,24(sp) - 10428: 01013b03 ld s6,16(sp) - 1042c: 00813b83 ld s7,8(sp) - 10430: 00013c03 ld s8,0(sp) - 10434: 05010113 addi sp,sp,80 - 10438: 00008067 ret - 1043c: 00892783 lw a5,8(s2) - 10440: 0084b703 ld a4,8(s1) - 10444: fff7879b addiw a5,a5,-1 - 10448: 06878263 beq a5,s0,104ac <__call_exitprocs+0x114> - 1044c: 0004b423 sd zero,8(s1) - 10450: fa0708e3 beqz a4,10400 <__call_exitprocs+0x68> - 10454: 31092783 lw a5,784(s2) - 10458: 008a96bb sllw a3,s5,s0 - 1045c: 00892c03 lw s8,8(s2) - 10460: 00d7f7b3 and a5,a5,a3 - 10464: 0007879b sext.w a5,a5 - 10468: 02079263 bnez a5,1048c <__call_exitprocs+0xf4> - 1046c: 000700e7 jalr a4 - 10470: 00892703 lw a4,8(s2) - 10474: 1f8a3783 ld a5,504(s4) - 10478: 01871463 bne a4,s8,10480 <__call_exitprocs+0xe8> - 1047c: f92782e3 beq a5,s2,10400 <__call_exitprocs+0x68> - 10480: f80786e3 beqz a5,1040c <__call_exitprocs+0x74> - 10484: 00078913 mv s2,a5 - 10488: f59ff06f j 103e0 <__call_exitprocs+0x48> - 1048c: 31492783 lw a5,788(s2) - 10490: 1084b583 ld a1,264(s1) - 10494: 00d7f7b3 and a5,a5,a3 - 10498: 0007879b sext.w a5,a5 - 1049c: 00079c63 bnez a5,104b4 <__call_exitprocs+0x11c> - 104a0: 000b0513 mv a0,s6 - 104a4: 000700e7 jalr a4 - 104a8: fc9ff06f j 10470 <__call_exitprocs+0xd8> - 104ac: 00892423 sw s0,8(s2) - 104b0: fa1ff06f j 10450 <__call_exitprocs+0xb8> - 104b4: 00058513 mv a0,a1 - 104b8: 000700e7 jalr a4 - 104bc: fb5ff06f j 10470 <__call_exitprocs+0xd8> - -00000000000104c0 <__libc_fini_array>: - 104c0: fe010113 addi sp,sp,-32 - 104c4: 00813823 sd s0,16(sp) - 104c8: 000117b7 lui a5,0x11 - 104cc: 00011437 lui s0,0x11 - 104d0: 62878793 addi a5,a5,1576 # 11628 <__do_global_dtors_aux_fini_array_entry> - 104d4: 63040413 addi s0,s0,1584 # 11630 - 104d8: 40f40433 sub s0,s0,a5 - 104dc: 00913423 sd s1,8(sp) - 104e0: 00113c23 sd ra,24(sp) - 104e4: 40345493 srai s1,s0,0x3 - 104e8: 02048063 beqz s1,10508 <__libc_fini_array+0x48> - 104ec: ff840413 addi s0,s0,-8 - 104f0: 00f40433 add s0,s0,a5 - 104f4: 00043783 ld a5,0(s0) - 104f8: fff48493 addi s1,s1,-1 - 104fc: ff840413 addi s0,s0,-8 - 10500: 000780e7 jalr a5 - 10504: fe0498e3 bnez s1,104f4 <__libc_fini_array+0x34> - 10508: 01813083 ld ra,24(sp) - 1050c: 01013403 ld s0,16(sp) - 10510: 00813483 ld s1,8(sp) - 10514: 02010113 addi sp,sp,32 - 10518: 00008067 ret - -000000000001051c : - 1051c: 00050593 mv a1,a0 - 10520: 00000693 li a3,0 - 10524: 00000613 li a2,0 - 10528: 00000513 li a0,0 - 1052c: 0040006f j 10530 <__register_exitproc> - -0000000000010530 <__register_exitproc>: - 10530: f481b703 ld a4,-184(gp) # 11d78 <_global_impure_ptr> - 10534: 1f873783 ld a5,504(a4) - 10538: 06078063 beqz a5,10598 <__register_exitproc+0x68> - 1053c: 0087a703 lw a4,8(a5) - 10540: 01f00813 li a6,31 - 10544: 08e84663 blt a6,a4,105d0 <__register_exitproc+0xa0> - 10548: 02050863 beqz a0,10578 <__register_exitproc+0x48> - 1054c: 00371813 slli a6,a4,0x3 - 10550: 01078833 add a6,a5,a6 - 10554: 10c83823 sd a2,272(a6) - 10558: 3107a883 lw a7,784(a5) - 1055c: 00100613 li a2,1 - 10560: 00e6163b sllw a2,a2,a4 - 10564: 00c8e8b3 or a7,a7,a2 - 10568: 3117a823 sw a7,784(a5) - 1056c: 20d83823 sd a3,528(a6) - 10570: 00200693 li a3,2 - 10574: 02d50863 beq a0,a3,105a4 <__register_exitproc+0x74> - 10578: 00270693 addi a3,a4,2 - 1057c: 00369693 slli a3,a3,0x3 - 10580: 0017071b addiw a4,a4,1 - 10584: 00e7a423 sw a4,8(a5) - 10588: 00d787b3 add a5,a5,a3 - 1058c: 00b7b023 sd a1,0(a5) - 10590: 00000513 li a0,0 - 10594: 00008067 ret - 10598: 20070793 addi a5,a4,512 - 1059c: 1ef73c23 sd a5,504(a4) - 105a0: f9dff06f j 1053c <__register_exitproc+0xc> - 105a4: 3147a683 lw a3,788(a5) - 105a8: 00000513 li a0,0 - 105ac: 00c6e6b3 or a3,a3,a2 - 105b0: 30d7aa23 sw a3,788(a5) - 105b4: 00270693 addi a3,a4,2 - 105b8: 00369693 slli a3,a3,0x3 - 105bc: 0017071b addiw a4,a4,1 - 105c0: 00e7a423 sw a4,8(a5) - 105c4: 00d787b3 add a5,a5,a3 - 105c8: 00b7b023 sd a1,0(a5) - 105cc: 00008067 ret - 105d0: fff00513 li a0,-1 - 105d4: 00008067 ret - -00000000000105d8 <_exit>: - 105d8: 05d00893 li a7,93 - 105dc: 00000073 ecall - 105e0: 00054463 bltz a0,105e8 <_exit+0x10> - 105e4: 0000006f j 105e4 <_exit+0xc> - 105e8: ff010113 addi sp,sp,-16 - 105ec: 00813023 sd s0,0(sp) - 105f0: 00050413 mv s0,a0 - 105f4: 00113423 sd ra,8(sp) - 105f8: 4080043b negw s0,s0 - 105fc: 00c000ef jal ra,10608 <__errno> - 10600: 00852023 sw s0,0(a0) - 10604: 0000006f j 10604 <_exit+0x2c> - -0000000000010608 <__errno>: - 10608: f581b503 ld a0,-168(gp) # 11d88 <_impure_ptr> - 1060c: 00008067 ret - -Disassembly of section .eh_frame: - -0000000000011610 <__FRAME_END__>: - 11610: 0000 .2byte 0x0 - ... - -Disassembly of section .init_array: - -0000000000011618 <__init_array_start>: - 11618: 0118 .2byte 0x118 - 1161a: 0001 .2byte 0x1 - 1161c: 0000 .2byte 0x0 - ... - -0000000000011620 <__frame_dummy_init_array_entry>: - 11620: 01c0 .2byte 0x1c0 - 11622: 0001 .2byte 0x1 - 11624: 0000 .2byte 0x0 - ... - -Disassembly of section .fini_array: - -0000000000011628 <__do_global_dtors_aux_fini_array_entry>: - 11628: 017c .2byte 0x17c - 1162a: 0001 .2byte 0x1 - 1162c: 0000 .2byte 0x0 - ... - -Disassembly of section .data: - -0000000000011630 : - ... - 11638: 1b68 .2byte 0x1b68 - 1163a: 0001 .2byte 0x1 - 1163c: 0000 .2byte 0x0 - 1163e: 0000 .2byte 0x0 - 11640: 1c18 .2byte 0x1c18 - 11642: 0001 .2byte 0x1 - 11644: 0000 .2byte 0x0 - 11646: 0000 .2byte 0x0 - 11648: 1cc8 .2byte 0x1cc8 - 1164a: 0001 .2byte 0x1 - ... - 11718: 0001 .2byte 0x1 - 1171a: 0000 .2byte 0x0 - 1171c: 0000 .2byte 0x0 - 1171e: 0000 .2byte 0x0 - 11720: 330e .2byte 0x330e - 11722: abcd .2byte 0xabcd - 11724: 1234 .2byte 0x1234 - 11726: e66d .2byte 0xe66d - 11728: deec .2byte 0xdeec - 1172a: 0005 .2byte 0x5 - 1172c: 0000000b .4byte 0xb - ... - -Disassembly of section .sdata: - -0000000000011d78 <_global_impure_ptr>: - 11d78: 1630 .2byte 0x1630 - 11d7a: 0001 .2byte 0x1 - 11d7c: 0000 .2byte 0x0 - ... - -0000000000011d80 <__dso_handle>: - ... - -0000000000011d88 <_impure_ptr>: - 11d88: 1630 .2byte 0x1630 - 11d8a: 0001 .2byte 0x1 - 11d8c: 0000 .2byte 0x0 - ... - -Disassembly of section .bss: - -0000000000011d90 : - ... - -0000000000011d98 : - ... - -Disassembly of section .comment: - -0000000000000000 <.comment>: - 0: 3a434347 .4byte 0x3a434347 - 4: 2820 .2byte 0x2820 - 6: 2029 .2byte 0x2029 - 8: 3231 .2byte 0x3231 - a: 322e .2byte 0x322e - c: 302e .2byte 0x302e - e: 4700 .2byte 0x4700 - 10: 203a4343 .4byte 0x203a4343 - 14: 4728 .2byte 0x4728 - 16: 554e .2byte 0x554e - 18: 2029 .2byte 0x2029 - 1a: 3231 .2byte 0x3231 - 1c: 322e .2byte 0x322e - 1e: 302e .2byte 0x302e - ... - -Disassembly of section .riscv.attributes: - -0000000000000000 <.riscv.attributes>: - 0: 2041 .2byte 0x2041 - 2: 0000 .2byte 0x0 - 4: 7200 .2byte 0x7200 - 6: 7369 .2byte 0x7369 - 8: 01007663 bgeu zero,a6,14 - c: 0016 .2byte 0x16 - e: 0000 .2byte 0x0 - 10: 1004 .2byte 0x1004 - 12: 7205 .2byte 0x7205 - 14: 3676 .2byte 0x3676 - 16: 6934 .2byte 0x6934 - 18: 7032 .2byte 0x7032 - 1a: 5f30 .2byte 0x5f30 - 1c: 326d .2byte 0x326d - 1e: 3070 .2byte 0x3070 - ... diff --git a/memory.txt b/memory.txt deleted file mode 100644 index 114b58f..0000000 --- a/memory.txt +++ /dev/null @@ -1,8 +0,0 @@ -4000 1b8 -00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 00 00 00 73 00 00 80 67 01 30 08 93 00 00 00 73 00 00 80 67 01 40 08 93 00 00 00 73 00 00 80 67 01 50 08 93 00 00 00 73 00 00 80 67 01 60 08 93 00 00 00 73 00 00 80 67 01 70 08 93 00 00 00 73 00 00 80 67 01 80 08 93 00 00 00 73 00 00 80 67 01 90 08 93 00 00 00 73 00 00 80 67 01 a0 08 93 00 00 00 73 00 00 80 67 01 b0 08 93 00 00 00 73 00 00 80 67 01 c0 08 93 00 00 00 73 00 00 80 67 01 d0 08 93 00 00 00 73 00 00 80 67 02 10 08 93 00 00 00 73 00 00 80 67 02 20 08 93 00 00 00 73 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -400000 1450 -fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fd 84 37 83 fe f4 34 23 fe 84 37 83 00 07 80 e7 00 00 05 13 ff c0 40 97 ff 80 80 e7 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 11 3c 23 00 81 38 23 02 01 04 13 fe a4 34 23 fe b4 30 23 00 40 07 b7 00 07 87 93 00 07 87 9b fe 04 37 03 00 07 07 1b 00 07 06 13 00 07 85 93 fe 84 35 03 ff c0 40 97 01 c0 80 e7 00 05 07 93 00 07 85 13 01 81 30 83 01 01 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 24 23 fe 04 22 23 0b 40 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 92 63 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 98 63 00 10 07 93 fe f4 24 23 fe 04 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b f4 07 84 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fe 04 26 23 fe 04 24 23 fd 84 37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 87 1b fe c4 27 83 00 07 87 9b 00 e7 98 63 00 40 47 b7 01 87 85 13 28 d0 00 ef fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 00 07 87 13 fd 44 27 83 00 07 07 1b 00 07 87 9b ea f7 42 e3 00 00 00 13 00 00 00 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 f5 01 01 13 0a 81 34 23 0b 01 04 13 f6 a4 34 23 00 05 87 93 f4 c4 3c 23 f4 d4 38 23 f6 f4 22 23 f6 84 37 83 00 07 8c 63 f5 84 37 83 00 07 88 63 f6 44 27 83 00 07 87 9b 00 07 d6 63 ff f0 07 93 17 90 00 6f fe 04 24 23 fe 04 26 23 14 d0 00 6f fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 87 13 02 50 07 93 0c f7 1e e3 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b 00 07 86 93 02 50 07 13 04 e6 8c 63 00 07 86 93 02 50 07 13 00 e6 ce e3 00 07 86 93 07 80 07 13 00 d7 48 e3 00 07 86 93 06 30 07 13 00 e6 c2 e3 f9 d7 86 9b 00 06 87 1b 01 50 07 93 7e e7 ea 63 02 06 97 93 02 07 d7 93 00 27 97 13 00 40 47 b7 02 87 87 93 00 f7 07 b3 00 07 a7 83 00 07 80 67 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 01 d0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fe f4 22 23 fe 04 20 23 fe 44 27 83 00 07 87 9b 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 67 bb f8 f4 2c 23 f9 84 27 83 41 f7 d7 9b f9 84 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2c 23 f9 84 27 83 0f f7 f7 13 fe 04 27 83 00 17 86 9b fe d4 20 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 8c 23 fe 44 27 83 00 07 87 13 00 a0 07 93 02 f7 47 bb fe f4 22 23 fe 44 27 83 00 07 87 9b f8 07 98 e3 fe 04 27 83 ff f7 87 9b fe f4 20 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fe 04 27 03 ff 07 07 13 00 87 07 33 f9 87 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 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f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 08 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 05 00 00 6f 00 00 00 13 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 ea 07 94 63 f6 84 37 83 00 07 80 23 fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 fe 04 26 23 00 10 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -404000 80 -00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 -4000 -405270 \ No newline at end of file diff --git a/memoryComp.txt b/memoryComp.txt deleted file mode 100644 index 0d30a7a..0000000 --- a/memoryComp.txt +++ /dev/null @@ -1,8 +0,0 @@ -4000 1b8 -00 3f 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c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 85 93 00 40 47 b7 01 07 85 13 2c d0 00 ef fe c4 27 83 00 17 87 9b 00 07 87 9b 00 07 87 9b 00 f7 f7 93 00 07 87 9b 00 07 8e 63 fd 44 27 83 ff f7 87 9b 00 07 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fe 84 27 83 00 17 87 9b fe f4 24 23 fe 04 27 83 ff f7 87 9b fe f4 20 23 fe 04 27 83 00 07 87 9b fa 07 d4 e3 6d c0 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 83 f5 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 1b 00 07 06 93 06 40 07 93 00 f6 88 63 07 80 07 93 12 f7 0c 63 2d c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 3c 23 fc 04 2a 23 fd 84 37 83 02 07 de 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 d0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 84 37 03 00 a0 07 93 02 f7 67 b3 f8 f4 2e 23 f9 c4 27 83 41 f7 d7 9b f9 c4 27 03 00 e7 c7 33 40 f7 07 bb f8 f4 2e 23 f9 c4 27 83 0f f7 f7 13 fd 44 27 83 00 17 86 9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 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00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 -4000 -405270 \ No newline at end of file diff --git a/memoryDiv.txt b/memoryDiv.txt deleted file mode 100644 index 682294e..0000000 --- a/memoryDiv.txt +++ /dev/null @@ -1,8 +0,0 @@ -4000 1b8 -00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 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9b fc d4 2a 23 03 07 07 1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 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fe 84 27 83 00 07 85 13 0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 01 01 13 0c 11 3c 23 0c 81 38 23 0e 01 04 13 f2 84 07 93 00 00 06 13 0c 80 05 93 00 07 85 13 ff c0 30 97 c7 80 80 e7 f2 84 07 93 00 07 85 13 ff 9f e0 ef 00 05 07 93 00 07 85 13 0d 81 30 83 0d 01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 40 07 93 fe f4 26 23 00 20 07 93 fe f4 24 23 fe c4 27 83 00 07 87 13 fe 84 27 83 02 f7 57 bb fe f4 26 23 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -404000 80 -00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 -4000 -405270 \ No newline at end of file diff --git a/memoryIf.txt b/memoryIf.txt deleted file mode 100644 index 8b0da1e..0000000 --- a/memoryIf.txt +++ /dev/null @@ -1,8 +0,0 @@ -4000 1b8 -00 3f d0 97 41 00 80 e7 00 00 05 13 01 40 00 ef 00 00 80 67 00 00 08 93 00 00 00 73 00 00 80 67 00 10 08 93 00 00 00 73 00 00 80 67 00 20 08 93 00 00 00 73 00 00 80 67 00 30 08 93 00 00 00 73 00 00 80 67 00 40 08 93 00 00 00 73 00 00 80 67 00 50 08 93 00 00 00 73 00 00 80 67 00 60 08 93 00 00 00 73 00 00 80 67 00 70 08 93 00 00 00 73 00 00 80 67 00 80 08 93 00 00 00 73 00 00 80 67 00 90 08 93 00 00 00 73 00 00 80 67 01 f0 08 93 00 00 00 73 00 00 80 67 00 a0 08 93 00 00 00 73 00 00 80 67 01 e0 08 93 00 00 00 73 00 00 80 67 00 b0 08 93 00 00 00 73 00 00 80 67 00 c0 08 93 00 00 00 73 00 00 80 67 00 d0 08 93 00 00 00 73 00 00 80 67 00 e0 08 93 00 00 00 73 00 00 80 67 00 f0 08 93 00 00 00 73 00 00 80 67 01 00 08 93 00 00 00 73 00 00 80 67 02 00 08 93 00 00 00 73 00 00 80 67 01 10 08 93 00 00 00 73 00 00 80 67 01 20 08 93 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37 83 06 07 86 63 fd 04 37 83 06 07 82 63 04 c0 00 6f fe c4 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 07 96 63 00 10 07 93 fe f4 24 23 fe c4 27 83 fd 04 37 03 00 f7 07 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b fa 07 88 e3 fd 84 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 01 00 00 6f fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 67 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 fe 07 92 e3 fe c4 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 fc b4 38 23 fd 84 35 03 f9 9f f0 ef 00 05 07 93 00 07 87 9b fe f4 24 23 fd 04 35 03 f8 5f f0 ef 00 05 07 93 00 07 87 9b fe f4 22 23 fe 84 27 83 fe f4 26 23 04 40 00 6f fe c4 27 83 00 07 87 13 fe 84 27 83 40 f7 07 bb 00 07 87 9b 00 07 87 13 fd 04 37 83 00 e7 87 33 fe c4 27 83 fd 84 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 44 27 83 00 07 87 13 fe 84 27 83 00 f7 07 bb 00 07 87 1b fe c4 27 83 00 07 87 9b fa f7 52 e3 fd 84 37 83 00 07 85 13 02 81 30 83 02 01 34 03 03 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 06 00 07 93 02 e7 d2 63 fe c4 27 83 00 07 87 1b 07 a0 07 93 00 e7 ca 63 fe c4 27 83 fe 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 1b 05 a0 07 93 02 e7 c2 63 fe c4 27 83 00 07 87 1b 04 00 07 93 00 e7 da 63 fe c4 27 83 02 07 87 9b 00 07 87 9b 00 80 00 6f fe c4 27 83 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 fe 04 20 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 d0 07 93 0c f7 10 63 00 10 07 93 fe f4 20 23 00 10 07 93 fe f4 26 23 0a c0 00 6f fe c4 27 83 fd 84 37 03 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f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 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34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 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1b 0f f7 77 13 ff 07 87 93 00 87 87 b3 f8 e7 80 23 fd 84 37 03 00 a0 07 93 02 f7 47 b3 fc f4 3c 23 fd 84 37 83 f8 07 9e e3 fd 44 27 83 ff f7 87 9b fc f4 2a 23 05 40 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fd 44 27 03 ff 07 07 13 00 87 07 33 f8 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 44 27 83 ff f7 87 9b fc f4 2a 23 fd 44 27 83 00 07 87 9b fa 07 d4 e3 26 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fa f4 34 23 fc 04 26 23 fc 04 28 23 13 40 00 6f fd 04 27 83 00 27 97 9b 00 07 87 9b 00 07 87 13 fa 84 37 83 00 e7 97 b3 fa f4 30 23 fa 04 37 83 03 c7 d7 93 fa f4 30 23 fa 04 37 83 00 f7 f7 93 fa f4 30 23 fa 04 37 83 04 07 96 63 fc c4 27 83 00 07 87 9b 0e 07 80 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 40 00 6f 00 10 07 93 fc f4 26 23 fa 04 37 03 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fa 04 37 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fd 04 27 83 00 17 87 9b fc f4 28 23 fd 04 27 83 00 07 87 1b 00 f0 07 93 ec e7 f2 e3 fc c4 27 83 00 07 87 9b 0e 07 9c 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0b c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 02 50 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 06 c0 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fe c4 27 83 f5 84 37 03 00 f7 07 33 f6 84 37 83 00 17 86 93 f6 d4 34 23 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 00 80 00 6f 00 00 00 13 30 c0 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 f8 f4 2a 23 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 f9 44 27 03 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 2b 80 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 b7 83 fc f4 30 23 fc 04 37 83 04 07 9e 63 00 40 47 b7 02 07 87 93 fc f4 30 23 04 c0 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 de 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 fc 04 37 03 00 07 47 03 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fc 04 37 83 00 17 87 93 fc f4 30 23 fc 04 37 83 00 07 c7 83 fa 07 98 e3 23 40 00 6f f5 04 37 83 00 87 87 13 f4 e4 38 23 00 07 a7 83 fa f4 2a 23 fa 04 2c 23 fa 04 2e 23 13 80 00 6f fb c4 27 83 00 27 97 9b 00 07 87 9b fb 44 27 03 00 f7 17 bb fa f4 28 23 fb 04 27 83 01 c7 d7 9b fa f4 28 23 fb 04 27 83 00 f7 f7 93 fa f4 28 23 fb 04 27 83 00 07 87 9b 04 07 96 63 fb 84 27 83 00 07 87 9b 0e 07 82 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 00 e7 dc 63 f6 84 37 83 00 17 87 13 f6 e4 34 23 03 00 07 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 0a 80 00 6f 00 10 07 93 fa f4 2c 23 fb 04 27 83 00 07 87 1b 00 90 07 93 04 e7 e6 63 f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 03 07 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 04 80 00 6f f6 44 27 83 ff f7 87 9b 00 07 87 1b fe 84 27 83 00 07 87 9b 02 e7 d2 63 fb 04 27 83 0f f7 f7 13 f6 84 37 83 00 17 86 93 f6 d4 34 23 05 77 07 1b 0f f7 77 13 00 e7 80 23 fe 84 27 83 00 17 87 9b fe f4 24 23 fb c4 27 83 00 17 87 9b fa f4 2e 23 fb c4 27 83 00 07 87 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0a 81 34 03 0b 01 01 13 00 00 80 67 f9 01 01 13 02 11 3c 23 02 81 38 23 04 01 04 13 fc a4 3c 23 fc c4 34 23 00 d4 34 23 00 e4 38 23 00 f4 3c 23 03 04 30 23 03 14 34 23 00 05 87 93 fc f4 2a 23 03 04 07 93 fc f4 30 23 fc 04 37 83 fd 87 87 93 fe f4 34 23 fe 84 37 03 fd 44 27 83 00 07 06 93 fc 84 36 03 00 07 85 93 fd 84 35 03 dd 8f f0 ef 00 05 07 93 fc f4 2a 23 fd 44 27 83 00 07 85 13 03 81 30 83 03 01 34 03 07 01 01 13 00 00 80 67 ec 01 01 13 0e 11 3c 23 0e 81 38 23 10 01 04 13 f0 a4 34 23 00 b4 34 23 00 c4 38 23 00 d4 3c 23 02 e4 30 23 02 f4 34 23 03 04 38 23 03 14 3c 23 04 04 07 93 f0 f4 30 23 f0 04 37 83 fc 87 87 93 fe f4 30 23 fe 04 37 03 f1 84 07 93 00 07 06 93 f0 84 36 03 0c 80 05 93 00 07 85 13 d5 8f f0 ef 00 05 07 93 fe f4 26 23 fe c4 27 83 00 07 87 13 0c 70 07 93 00 e7 f6 63 0c 70 07 93 fe f4 26 23 fe c4 27 83 00 07 87 9b 02 f0 50 63 fe c4 27 03 f1 84 07 93 00 10 06 13 00 07 05 93 00 07 85 13 ff c0 30 97 cc 00 80 e7 00 00 00 13 0f 81 30 83 0f 01 34 03 14 01 01 13 00 00 80 67 f2 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83 02 07 8e 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 02 f0 07 93 02 e7 f0 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 13 03 90 07 93 00 e7 f8 63 00 10 07 93 fe f4 24 23 05 40 00 6f fe 44 27 83 00 07 87 13 00 07 07 93 00 27 97 9b 00 e7 87 bb 00 17 97 9b fe f4 22 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 07 87 9b fd 07 87 9b 00 07 87 9b fe 44 27 03 00 f7 07 bb fe f4 22 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe 84 27 83 00 07 87 9b f4 07 88 e3 fe 04 27 83 00 07 87 9b 00 07 8a 63 fe 44 27 83 40 f0 07 bb 00 07 87 9b 00 80 00 6f fe 44 27 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fc f4 3c 23 fc 04 37 83 fc f4 38 23 fe 04 26 23 fe 04 24 23 fe 04 22 23 08 00 00 6f fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 f7 7a 63 00 10 07 93 fe f4 24 23 ff f0 07 93 fe f4 26 23 fe 44 27 83 fd 84 37 03 00 f7 07 b3 00 07 c6 83 fe 44 27 83 fd 04 37 03 00 f7 07 b3 00 07 c7 83 00 06 87 13 00 e7 fa 63 00 10 07 93 fe f4 24 23 00 10 07 93 fe f4 26 23 fe 44 27 83 00 17 87 9b fe f4 22 23 fe 84 27 83 00 07 87 9b 00 07 9a 63 fe 44 27 03 fb c4 27 83 00 07 87 9b f6 f7 66 e3 fe c4 27 83 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fb 01 01 13 04 81 34 23 05 01 04 13 fc a4 34 23 fc b4 30 23 00 06 07 93 fa f4 2e 23 fc 84 37 83 fe f4 30 23 fc 04 37 83 fc f4 3c 23 fe 04 26 23 fe 04 37 83 04 07 8a 63 fd 84 37 83 04 07 86 63 03 00 00 6f fe c4 27 83 fd 84 37 03 00 f7 07 33 fe c4 27 83 fe 04 36 83 00 f6 87 b3 00 07 47 03 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fb c4 27 83 00 07 87 9b fc f7 64 e3 fe 04 37 83 00 80 00 6f 00 00 07 93 00 07 85 13 04 81 34 03 05 01 01 13 00 00 80 67 fd 01 01 13 02 81 34 23 03 01 04 13 fc a4 3c 23 00 05 87 93 00 06 07 13 fc f4 2a 23 00 07 07 93 fc f4 28 23 fd 84 37 83 fe f4 30 23 fe 04 26 23 02 80 00 6f fe c4 27 83 fe 04 37 03 00 f7 07 b3 fd 44 27 03 0f f7 77 13 00 e7 80 23 fe c4 27 83 00 17 87 9b fe f4 26 23 fe c4 27 03 fd 04 27 83 00 07 87 9b fc f7 68 e3 fe 04 37 83 00 07 85 13 02 81 34 03 03 01 01 13 00 00 80 67 fd 01 01 13 02 11 34 23 02 81 30 23 03 01 04 13 fc a4 3c 23 00 05 87 93 fc f4 2a 23 fe 04 26 23 14 c0 00 6f fe c4 27 83 00 f7 f7 93 00 07 87 9b 02 07 92 63 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 85 93 00 40 47 b7 00 07 85 13 39 d0 00 ef 02 00 00 6f fe c4 27 83 00 77 f7 93 00 07 87 9b 00 07 98 63 00 40 47 b7 00 87 85 13 37 d0 00 ef fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 47 d7 9b fe f4 05 a3 fe b4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe b4 47 83 03 07 87 9b fe f4 05 a3 01 00 00 6f fe b4 47 83 05 77 87 9b fe f4 05 a3 fe b4 47 83 fe f4 00 23 fe c4 27 83 fd 84 37 03 00 f7 07 b3 00 07 c7 83 00 f7 f7 93 fe f4 05 23 fe a4 47 83 0f f7 f7 13 00 90 07 93 00 e7 ea 63 fe a4 47 83 03 07 87 9b fe f4 05 23 01 00 00 6f fe a4 47 83 05 77 87 9b fe f4 05 23 fe a4 47 83 fe f4 00 a3 fe 04 01 23 fe 04 07 93 00 07 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01 34 03 0e 01 01 13 00 00 80 67 fe 01 01 13 00 81 3c 23 02 01 04 13 fe 04 26 23 fe c4 27 83 00 07 87 1b 00 10 07 93 00 f7 1c 63 00 10 07 93 fe f4 26 23 00 00 00 13 00 00 07 93 00 80 00 6f 00 00 07 93 00 07 85 13 01 81 34 03 02 01 01 13 00 00 80 67 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -404000 80 -00 09 78 25 00 00 00 00 00 20 20 20 00 00 00 00 00 20 73 25 00 00 00 00 00 00 00 0a 00 00 00 00 6c 75 6e 28 00 00 29 6c 00 40 0e f8 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 09 e8 00 40 11 7c 00 40 11 7c 00 40 0b 28 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f 4c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 11 7c 00 40 0f d0 -4000 -405270 \ No newline at end of file diff --git a/old_section.txt b/old_section.txt deleted file mode 100644 index 21571c8..0000000 --- a/old_section.txt +++ /dev/null @@ -1,17 +0,0 @@ -fe010113 -00813c23 -02010413 -fe042623 -00100793 -fef42423 -fec42783 -00078713 -fe842783 -00f707bb -fef42623 -00000013 -01813403 -02010113 -00008067 -0 -0 \ No newline at end of file diff --git a/test_file_section.txt b/test_file_section.txt deleted file mode 100644 index 81b6acd..0000000 --- a/test_file_section.txt +++ /dev/null @@ -1,2 +0,0 @@ -130101FE233C8100 -13040102232604FE