diff --git a/src/simulator/print.rs b/src/simulator/print.rs
index 6e18925..451d3ef 100644
--- a/src/simulator/print.rs
+++ b/src/simulator/print.rs
@@ -5,7 +5,7 @@ use super::global::*;
 
 const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
 const NAMES_OPI: [&str; 8]  = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
-const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"];
+const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"];
 const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
 const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
 const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
@@ -13,7 +13,7 @@ const NAMES_OPW: [&str; 8]  = ["addw", "sllw", "", "", "", "srw", "", ""];
 const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
 
 // Register name mapping
-const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", // fp ou s0 ?
+const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
 "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
 "t3", "t4", "t5", "t6"];
@@ -95,10 +95,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
                 } else {
                     format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
                 }
-            } else if ins.funct3 == RISCV_OPIW_SLLIW {
-                format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
             } else {
-                format!("{}\t{},{},{}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
+                format!("{}\t{},{},0x{:x}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
             }
         },
         RISCV_OPW => {
@@ -216,8 +214,8 @@ mod test {
         let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
         let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
         let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
-        assert_eq!("addiw\tt3,a7,0", print::print(addiw, 0));
-        assert_eq!("slli\tt3,a7,a6", print::print(slliw, 0));
+        assert_eq!("addiw\tt3,a7,0x0", print::print(addiw, 0));
+        assert_eq!("slliw\tt3,a7,0x10", print::print(slliw, 0));
         assert_eq!("srai\tt3,a7,17", print::print(srai, 0));
 
     }
@@ -259,7 +257,10 @@ mod test {
         assert_eq!("lw	a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));          	
         assert_eq!("addi	a4,a5,0", print::print(decode::decode(0x00078713), 0));          	
         assert_eq!("lw	a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));          	
-        //Waiting for mulw implementation assert_eq!("mulw	a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));          	
+        
+        //Waiting for mulw implementation 
+        assert_eq!("mulw	a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));          	
+        
         assert_eq!("sw	a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));          	
         assert_eq!("lw	a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));          	
         assert_eq!("addi	a4,a5,0", print::print(decode::decode(0x00078713), 0));          	
@@ -286,4 +287,34 @@ mod test {
         assert_eq!("blt	a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518));
     }
 
+    #[test]
+    fn test_mul_prog() {
+        assert_eq!("addi	sp,sp,-32", print::print(decode::decode(0xfe010113), 0));             
+        assert_eq!("sd	s0,24(sp)", print::print(decode::decode(0x00813c23), 0));
+        assert_eq!("addi	s0,sp,32", print::print(decode::decode(0x02010413), 0));
+        assert_eq!("addi	a5,zero,5", print::print(decode::decode(0x00500793), 0));
+        assert_eq!("sw	a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
+        assert_eq!("lw	a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
+        assert_eq!("addi	a4,a5,0", print::print(decode::decode(0x00078713), 0));
+        assert_eq!("addi	a5,a4,0", print::print(decode::decode(0x00070793), 0));
+        assert_eq!("slliw	a5,a5,0x2", print::print(decode::decode(0x0027979b), 0));
+        assert_eq!("addw	a5,a5,a4", print::print(decode::decode(0x00e787bb), 0));
+        assert_eq!("sw	a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
+        assert_eq!("lw	a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
+        assert_eq!("addi	a4,a5,0", print::print(decode::decode(0x00078713), 0));
+        assert_eq!("lw	a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
+        assert_eq!("mulw	a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));
+        assert_eq!("sw	a5,-28(s0)", print::print(decode::decode(0xfef42223), 0));
+        assert_eq!("lw	a5,-28(s0)", print::print(decode::decode(0xfe442783), 0));
+        assert_eq!("addi	a4,a5,0", print::print(decode::decode(0x00078713), 0));
+        assert_eq!("lw	a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
+        assert_eq!("divw	a5,a4,a5", print::print(decode::decode(0x02f747bb), 0));
+        assert_eq!("sw	a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
+        assert_eq!("addi	a5,zero,0", print::print(decode::decode(0x00000793), 0));
+        assert_eq!("addi	a0,a5,0", print::print(decode::decode(0x00078513), 0));
+        assert_eq!("ld	s0,24(sp)", print::print(decode::decode(0x01813403), 0));
+        assert_eq!("addi	sp,sp,32", print::print(decode::decode(0x02010113), 0));
+        assert_eq!("jalr	zero,0(ra)", print::print(decode::decode(0x00008067), 0));
+    }
+
 }
\ No newline at end of file