Moving files to simulator module
This commit is contained in:
Quentin Legot
383
src/simulator/machine.rs
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383
src/simulator/machine.rs
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@ -0,0 +1,383 @@
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use super::{decode::{Instruction, decode}, print::*};
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/// doit disparaitre
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const MEM_SIZE : usize= 4096;
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pub struct Machine {
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pub pc : u64,
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pub int_reg : [i64 ; 32],
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pub instructions : [u64 ; 100],
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pub main_memory : [u8 ; MEM_SIZE],
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pub shiftmask : [u64 ; 64]
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// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
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//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
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}
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impl Machine {
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pub fn _init_machine() -> Machine {
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let mut shiftmask : [u64 ; 64] = [0 ; 64];
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let mut value : u64 = 0xffffffff;
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value = (value << 32) + value;
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for i in 0..64 {
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shiftmask[i] = value;
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value = value >> 1;
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}
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Machine {
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pc : 0,
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instructions : [0 ; 100],
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int_reg : [0 ; 32],
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main_memory : [0 ; MEM_SIZE],
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shiftmask : shiftmask
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}
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}
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/// Read from main memory of the machine
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///
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/// ### Parameters
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///
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/// - **machine** which contains the main memory
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/// - **size** the number of bytes to read (1, 2, 4, 8)
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/// - **address** in the memory to read
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pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
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if size != 1 && size != 2 && size != 4 && size != 8 {
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println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
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}
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let mut ret : u64 = machine.main_memory[address] as u64;
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if size == 2 || size == 4 || size == 8 {
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ret = ret << 8;
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ret += machine.main_memory[address + 1] as u64;
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}
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if size == 4 || size == 8 {
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ret = ret << 8;
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ret += machine.main_memory[address + 2] as u64;
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}
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if size == 8 {
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ret = ret << 8;
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ret += machine.main_memory[address + 3] as u64;
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}
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return ret;
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}
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/// Execute the instructions table of a machine putted in param
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions
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pub fn run(machine : Machine){
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let mut m = machine;
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loop{
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Machine::one_instruction(&mut m);
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}
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}
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/// execute the current instruction
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions and a pc to the actual instruction
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pub fn one_instruction(machine :&mut Machine) {
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let mut unsigned_reg1 : u64 = 0;
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let mut unsigned_reg2 : u64 = 0;
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let mut long_result : i128 = 0;
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/*__int128 longResult;
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int32_t localDataa, localDatab;
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int64_t localLongResult;
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uint32_t localDataaUnsigned, localDatabUnsigned;
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int32_t localResult;
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float localFloat;
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uint64_t value;*/
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if machine.instructions.len() <= machine.pc as usize {
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println!("ERROR : number max of instructions rushed");
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return ;
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}
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let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
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match inst.opcode {
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RISCV_LUI => {
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machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64;
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},
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RISCV_AUIPC => {
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machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64;
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},
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RISCV_JAL => {
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machine.int_reg[inst.rd as usize] = machine.pc as i64;
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machine.pc += inst.imm21_1_signed as u64 - 4;
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},
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RISCV_JALR => {
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let tmp = machine.pc;
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machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
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machine.int_reg[inst.rd as usize] = tmp as i64;
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},
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//******************************************************************************************
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// Treatment for: BRANCH INSTRUCTIONS
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RISCV_BR => {
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match inst.funct3 {
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RISCV_BR_BEQ => {
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if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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RISCV_BR_BNE => {
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if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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RICV_BR_BLT => {
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if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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RICV_BR_BGE => {
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if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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RICV_BR_BLTU => {
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if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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RICV_BR_BGEU => {
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if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
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machine.pc += inst.imm13_signed as u64 - 4;
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}
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},
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_ => {
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println!("In BR switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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},
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//******************************************************************************************
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// Treatment for: LOAD INSTRUCTIONS
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RISCV_LD => {
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match inst.funct3 {
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RISCV_LD_LB => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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RISCV_LD_LH => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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RISCV_LD_LW => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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RISCV_LD_LD => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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// same thing three opration ?
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RISCV_LD_LBU => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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RISCV_LD_LHU => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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RISCV_LD_LWU => {
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machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
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},
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_ => {
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println!("In LD switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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},
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//TODO store instructions
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//******************************************************************************************
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// Treatment for: OPI INSTRUCTIONS
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RISCV_OPI => {
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match inst.funct3 {
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RISCV_OPI_ADDI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
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},
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RISCV_OPI_SLTI => {
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machine.int_reg[inst.rd as usize] =
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if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 };
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},
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RISCV_OPI_XORI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
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},
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RISCV_OPI_ORI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64;
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},
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RISCV_OPI_ANDI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64;
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},
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RISCV_OPI_SLLI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
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},
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RISCV_OPI_SRI => {
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if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
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machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64;
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} else { // SRAI
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;
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}
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}
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_ => { println!("{} inconnu", inst.funct3); }
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}
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},
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RISCV_OP => {
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if inst.funct7 == 1{
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match inst.funct3 {
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RISCV_OP_M_MUL => {
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long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
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machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64;
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},
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RISCV_OP_M_MULH => {
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long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
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},
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RISCV_OP_M_MULHSU => {
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unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
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long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
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machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
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},
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// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
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/*
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* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
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* WHAT DA HECK
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*/
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RISCV_OP_M_MULHU => {
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unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
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unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
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long_result = (unsigned_reg1 * unsigned_reg2) as i128;
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machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
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},
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RISCV_OP_M_DIV => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
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}
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_ => {
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println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
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}
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}
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} else {
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match inst.funct3 {
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RISCV_OP_ADD => {
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if (inst.funct7 == RISCV_OP_ADD_ADD) {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
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} else {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
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}
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},
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RISCV_OP_SLL => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
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},
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RISCV_OP_SLT => {
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if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
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machine.int_reg[inst.rd as usize] = 1;
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} else {
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machine.int_reg[inst.rd as usize] = 0;
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}
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},
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RISCV_OP_SLTU => {
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unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
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unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
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if unsigned_reg1 < unsigned_reg2 {
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machine.int_reg[inst.rd as usize] = 1;
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} else {
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machine.int_reg[inst.rd as usize] = 0;
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}
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},
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RISCV_OP_XOR => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
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},
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RISCV_OP_SR => {
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// RISCV_OP_SR_SRL inaccessible
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
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},
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RISCV_OP_OR => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
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},
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RISCV_OP_AND => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
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},
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_ => {
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println!("RISCV_OP undefined case\n");
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}
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}//LA
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}
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},
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//******************************************************************************************
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// Treatment for: OPW INSTRUCTIONS
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RISCV_OPW => {
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if inst.funct7 == 1 {
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let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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// Match case for multiplication operations (in standard extension RV32M)
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match inst.funct3 {
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RISCV_OPW_M_MULW => {
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machine.int_reg[inst.rd as usize] = localDataa * localDatab;
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},
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RISCV_OPW_M_DIVW => {
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machine.int_reg[inst.rd as usize] = localDataa / localDatab;
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},
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RISCV_OPW_M_DIVUW => {
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machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned;
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},
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RISCV_OPW_M_REMW => {
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machine.int_reg[inst.rd as usize] = localDataa % localDatab;
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},
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RISCV_OPW_M_REMUW => {
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machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned;
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},
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_ => {
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println!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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} else {
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let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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// Match case for base OP operation
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match inst.funct3 {
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RISCV_OPW_ADDSUBW => {
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if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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machine.int_reg[inst.rd as usize] = local_dataa + local_datab;
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} else { // SUBW
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machine.int_reg[inst.rd as usize] = local_dataa - local_datab;
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}
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},
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RISCV_OPW_SLLW => {
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machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f);
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},
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RISCV_OPW_SRW => {
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if inst.funct7 == RISCV_OPW_SRW_SRLW {
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machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64;
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} else { // SRAW
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machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
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}
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},
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_ => {
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println!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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}
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}
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_ => { println!("{} opcode non géré", inst.opcode)},
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}
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machine.pc += 4;
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}
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}
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#[cfg(test)]
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mod test {
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use super::Machine;
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}
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