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Merge branch 'thread_scheduler' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into thread_scheduler

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Samy Solhi 2023-03-29 16:15:53 +02:00
commit ac1f2287a2
6 changed files with 717 additions and 679 deletions
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95
src/simulator/decode.rs
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use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations voulues
#[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules)
#[derive(Debug)]
pub struct Instruction {
pub value : u64,
pub opcode : u8,
pub rs1 : u8,
pub rs2 : u8,
pub rs3 : u8,
pub rd : u8,
pub funct7 : u8,
pub funct7_smaller : u8,
pub funct3 : u8,
pub shamt : u8, // shamt = imm[5:0] or imm[4:0] (depend of opcode)
pub imm12_I : u16,
pub imm12_S : u16,
pub imm12_I_signed : i16,
pub imm12_S_signed : i16,
pub imm13 : i16,
pub imm13_signed : i16,
pub imm31_12 : u32,
pub imm21_1 : u32,
pub imm31_12_signed : i32,
pub imm21_1_signed : i32,
}
#[allow(non_snake_case)]
pub fn decode(val : u64) -> Instruction {
let value = val;
let opcode = (val & 0x7f) as u8;
let rs1 = ((val >> 15) & 0x1f) as u8;
let rs2 = ((val >> 20) & 0x1f) as u8;
let rs3 = ((val >> 27) & 0x1f) as u8;
let rd = ((val >> 7) & 0x1f) as u8;
let funct7 = ((val >> 25) & 0x7f) as u8;
let funct7_smaller = funct7 & 0x3e;
let funct3 = ((val >> 12) & 0x7) as u8;
let imm12_I = ((val >> 20) & 0xfff) as u16;
let imm12_S = (((val >> 20) & 0xfe0) + ((val >> 7) & 0x1f)) as u16;
let imm12_I_signed = if imm12_I >= 2048 { (Wrapping(imm12_I) - Wrapping(4096)).0 } else { imm12_I } as i16;
let imm12_S_signed = if imm12_S >= 2048 { (Wrapping(imm12_S) - Wrapping(4096)).0 } else { imm12_S } as i16;
let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) +
((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16;
let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 };
let imm31_12 = (val & 0xfffff000) as u32;
let imm31_12_signed = imm31_12 as i32;
let imm21_1 = ((val & 0xff000) + ((val >> 9) & 0x800) +
((val >> 20) & 0x7fe) + ((val >> 11) & 0x100000)) as u32;
let imm21_1_signed = if imm21_1 >= 1048576 { (Wrapping(imm21_1) - Wrapping(2097152)).0 } else { imm21_1 } as i32;
let shamt = ((val >> 20) & 0x3f) as u8;
Instruction {
value,
opcode,
rs1,
rs2,
rs3,
rd,
funct7,
funct7_smaller,
funct3,
imm12_I,
imm12_S,
imm12_I_signed,
imm12_S_signed,
imm13,
imm13_signed,
imm31_12,
imm31_12_signed,
imm21_1,
imm21_1_signed,
shamt
}
}

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src/simulator/instruction.rs Normal file
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use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations voulues
use super::global::*;
const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"];
const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
// Register name mapping
pub const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"];
const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
"ft8", "ft9", "ft10", "ft11"];
#[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules)
#[derive(Debug)]
pub struct Instruction {
pub value : u64,
pub opcode : u8,
pub rs1 : u8,
pub rs2 : u8,
pub rs3 : u8,
pub rd : u8,
pub funct7 : u8,
pub funct7_smaller : u8,
pub funct3 : u8,
pub shamt : u8, // shamt = imm[5:0] or imm[4:0] (depend of opcode)
pub imm12_I : u16,
pub imm12_S : u16,
pub imm12_I_signed : i16,
pub imm12_S_signed : i16,
pub imm13 : i16,
pub imm13_signed : i16,
pub imm31_12 : u32,
pub imm21_1 : u32,
pub imm31_12_signed : i32,
pub imm21_1_signed : i32,
}
#[allow(non_snake_case)]
pub fn decode(val : u64) -> Instruction {
let value = val;
let opcode = (val & 0x7f) as u8;
let rs1 = ((val >> 15) & 0x1f) as u8;
let rs2 = ((val >> 20) & 0x1f) as u8;
let rs3 = ((val >> 27) & 0x1f) as u8;
let rd = ((val >> 7) & 0x1f) as u8;
let funct7 = ((val >> 25) & 0x7f) as u8;
let funct7_smaller = funct7 & 0x3e;
let funct3 = ((val >> 12) & 0x7) as u8;
let imm12_I = ((val >> 20) & 0xfff) as u16;
let imm12_S = (((val >> 20) & 0xfe0) + ((val >> 7) & 0x1f)) as u16;
let imm12_I_signed = if imm12_I >= 2048 { (Wrapping(imm12_I) - Wrapping(4096)).0 } else { imm12_I } as i16;
let imm12_S_signed = if imm12_S >= 2048 { (Wrapping(imm12_S) - Wrapping(4096)).0 } else { imm12_S } as i16;
let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) +
((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16;
let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 };
let imm31_12 = (val & 0xfffff000) as u32;
let imm31_12_signed = imm31_12 as i32;
let imm21_1 = ((val & 0xff000) + ((val >> 9) & 0x800) +
((val >> 20) & 0x7fe) + ((val >> 11) & 0x100000)) as u32;
let imm21_1_signed = if imm21_1 >= 1048576 { (Wrapping(imm21_1) - Wrapping(2097152)).0 } else { imm21_1 } as i32;
let shamt = ((val >> 20) & 0x3f) as u8;
Instruction {
value,
opcode,
rs1,
rs2,
rs3,
rd,
funct7,
funct7_smaller,
funct3,
imm12_I,
imm12_S,
imm12_I_signed,
imm12_S_signed,
imm13,
imm13_signed,
imm31_12,
imm31_12_signed,
imm21_1,
imm21_1_signed,
shamt
}
}
pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let rd = ins.rd as usize;
let rs1 = ins.rs1 as usize;
let rs2 = ins.rs2 as usize;
let rs3 = ins.rs3 as usize;
match ins.opcode {
RISCV_OP => {
let name: &str;
if ins.funct7 == 1 { // Use mul array
name = NAMES_MUL[ins.funct3 as usize]
} else if ins.funct3 == RISCV_OP_ADD {
// Add or Sub
if ins.funct7 == RISCV_OP_ADD_ADD {
name = "add";
} else {
name = "sub";
}
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else {
name = NAMES_OP[ins.funct3 as usize];
}
format!("{}\t{},{},{}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
},
RISCV_OPI => {
// SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("srli\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
} else {
format!("srai\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
}
} else if ins.funct3 == RISCV_OPI_SLLI {
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt)
} else {
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
}
},
RISCV_LUI => {
format!("lui\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_AUIPC => {
format!("auipc\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_JAL => {
format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed))
},
RISCV_JALR => {
format!("jalr\t{},{:x}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
},
RISCV_BR => {
format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32))
},
RISCV_LD => {
format!("{}\t{},{}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
},
RISCV_ST => {
format!("{}\t{},{}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1])
},
RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srliw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else {
format!("{}\t{},{},0x{:x}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
}
},
RISCV_OPW => {
if ins.funct7 == 1 {
format!("{}w\t{},{},{}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else if ins.funct3 == RISCV_OP_ADD {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("subw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else {
format!("{}\t{},{},{}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
}
},
// RV32F Standard Extension
RISCV_FLW => {
format!("flw\t{},{},({})", REG_F[rd], ins.imm12_I_signed, REG_F[rs1])
},
RISCV_FSW => {
format!("fsw\t{},{},({})", REG_F[rs2], "OFFSET TODO", REG_F[rs1]) // TODO Offset in decode
},
RISCV_FMADD => {
format!("fmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FMSUB => {
format!("fmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FNMSUB => {
format!("fnmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FNMADD => {
format!("fnmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FP => {
match ins.funct7 {
RISCV_FP_ADD => {
format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_SUB => {
format!("{}\t{}{}{}", "fsub.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_MUL => {
format!("{}\t{}{}{}", "fmul.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_DIV => {
format!("{}\t{}{}{}", "fdiv.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_SQRT => {
format!("{}\t{}{}", "fsqrt.s", REG_F[rd], REG_F[rs1])
},
RISCV_FP_FSGN => {
match ins.funct3 {
RISCV_FP_FSGN_J => {
format!("{}\t{}{}{}", "fsgnj.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_FSGN_JN => {
format!("{}\t{}{}{}", "fsgnn.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_FSGN_JX => {
format!("{}\t{}{}{}", "fsgnx.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
_ => todo!("Unknown code")
}
},
RISCV_FP_MINMAX => {
if ins.funct3 == 0 {
format!("{}\t{}{}{}", "fmin.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else {
format!("{}\t{}{}{}", "fmax.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}
},
RISCV_FP_FCVTW => {
if rs2 == 0 {
format!("{}\t{}{}", "fcvt.w.s", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fcvt.wu.s", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FMVXFCLASS => {
if ins.funct3 == 0 {
format!("{}\t{}{}", "fmv.x.w", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fclass.s", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FCMP => {
if ins.funct3 == 0 {
format!("{}\t{}{}{}", "fle.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else if ins.funct3 == 1 {
format!("{}\t{}{}{}", "flt.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else {
format!("{}\t{}{}{}", "feq.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}
},
RISCV_FP_FCVTS => {
if rs2 == 0 {
format!("{}\t{}{}", "fcvt.s.w", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fcvt.s.wu", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FMVW => {
format!("{}\t{}{}", "fmv.w.x", REG_F[rd], REG_F[rs1])
},
_ => todo!("Unknown code")
}
},
RISCV_SYSTEM => {
"ecall".to_string()
},
_ => todo!("{:x} opcode non géré pc : {:x}, value : {:x}", ins.opcode, pc, ins.value) // Change todo! to panic! in the future, I put todo! because there's a lot of opcode currently not implemented
}
}
#[cfg(test)]
mod test {
#![allow(clippy::unusual_byte_groupings)]
use crate::simulator::instruction::*;
#[test]
fn test_op() {
let sub = decode(0b0100000_10000_10001_000_11100_0110011);
let add = decode(0b0000000_10000_10001_000_11100_0110011);
let xor = decode(0b0000000_10000_10001_100_11100_0110011);
let slr = decode(0b0000000_10000_10001_101_11100_0110011);
let sra = decode(0b0100000_10000_10001_101_11100_0110011);
assert_eq!("sub\tt3,a7,a6", print(sub, 0));
assert_eq!("xor\tt3,a7,a6", print(xor, 0));
assert_eq!("srl\tt3,a7,a6", print(slr, 0));
assert_eq!("sra\tt3,a7,a6", print(sra, 0));
assert_eq!("add\tt3,a7,a6", print(add, 0));
}
#[test]
fn test_opi() {
let addi = decode(0b0000000000_10001_000_11100_0010011);
let slli = decode(0b0000000000_10001_001_11100_0010011);
let slti = decode(0b0000000000_10001_010_11100_0010011);
let sltiu = decode(0b0000000000_10001_011_11100_0010011);
let xori = decode(0b_0000000000010001_100_11100_0010011);
let ori = decode(0b00000000000_10001_110_11100_0010011);
let andi = decode(0b000000000000_10001_111_11100_0010011);
assert_eq!("andi\tt3,a7,0", print(andi, 0));
assert_eq!("addi\tt3,a7,0", print(addi, 0));
assert_eq!("slli\tt3,a7,0", print(slli, 0));
assert_eq!("slti\tt3,a7,0", print(slti, 0));
assert_eq!("sltiu\tt3,a7,0", print(sltiu, 0));
assert_eq!("xori\tt3,a7,0", print(xori, 0));
assert_eq!("ori\tt3,a7,0", print(ori, 0));
}
#[test]
fn test_lui() {
let lui = decode(0b01110001000011111000_11100_0110111);
let lui_negatif = decode(0b11110001000011111000_11100_0110111);
assert_eq!("lui\tt3,710f8000", print(lui, 0));
assert_eq!("lui\tt3,f10f8000", print(lui_negatif, 0));
}
#[test]
fn test_ld() {
// imm rs1 f3 rd opcode
let lb = decode(0b010111110000_10001_000_11100_0000011);
let lh = decode(0b010111110000_10001_001_11100_0000011);
let lw = decode(0b010111110000_10001_010_11100_0000011);
let lbu = decode(0b010111110000_10001_100_11100_0000011);
let lhu = decode(0b010111110000_10001_101_11100_0000011);
let ld = decode(0b010111110000_10001_011_11100_0000011);
let lwu = decode(0b010111110000_10001_110_11100_0000011);
assert_eq!("lb\tt3,1520(a7)", print(lb, 0));
assert_eq!("lh\tt3,1520(a7)", print(lh, 0));
assert_eq!("lw\tt3,1520(a7)", print(lw, 0));
assert_eq!("lbu\tt3,1520(a7)", print(lbu, 0));
assert_eq!("lhu\tt3,1520(a7)", print(lhu, 0));
assert_eq!("ld\tt3,1520(a7)", print(ld, 0));
assert_eq!("lwu\tt3,1520(a7)", print(lwu, 0));
}
#[test]
fn test_opw() {
let addw: Instruction = decode(0b0000000_10000_10001_000_11100_0111011);
let sllw: Instruction = decode(0b0000000_10000_10001_001_11100_0111011);
let srlw: Instruction = decode(0b0000000_10000_10001_101_11100_0111011);
let sraw: Instruction = decode(0b0100000_10000_10001_101_11100_0111011);
assert_eq!("addw\tt3,a7,a6", print(addw, 0));
assert_eq!("sllw\tt3,a7,a6", print(sllw, 0));
assert_eq!("srlw\tt3,a7,a6", print(srlw, 0));
assert_eq!("sraw\tt3,a7,a6", print(sraw, 0));
}
#[test]
fn test_opwi() {
let addiw: Instruction =decode(0b000000000000_10001_000_11100_0011011);
let slliw: Instruction = decode(0b0000000_10000_10001_001_11100_0011011);
let srai: Instruction = decode(0b010000010001_10001_101_11100_0010011);
assert_eq!("addiw\tt3,a7,0x0", print(addiw, 0));
assert_eq!("slliw\tt3,a7,0x10", print(slliw, 0));
assert_eq!("srai\tt3,a7,17", print(srai, 0));
}
#[test]
fn test_br() {
let beq: Instruction = decode(0b0000000_10000_10001_000_00000_1100011);
let bne: Instruction = decode(0b0000000_10000_10001_001_00000_1100011);
let blt: Instruction = decode(0b0000000_10000_10001_100_00000_1100011);
let bge: Instruction = decode(0b0000000_10000_10001_101_00000_1100011);
let bge2: Instruction = decode(0x00f75863);
let bltu: Instruction = decode(0b0000000_10000_10001_110_00000_1100011);
let bgeu: Instruction = decode(0b0000000_10000_10001_111_00000_1100011);
assert_eq!("blt\ta7,a6,0", print(blt, 0));
assert_eq!("bge\ta7,a6,0", print(bge, 0));
assert_eq!("bge\ta4,a5,104d4", print(bge2, 0x104c4));
assert_eq!("bltu\ta7,a6,0", print(bltu, 0));
assert_eq!("bgeu\ta7,a6,0", print(bgeu, 0));
assert_eq!("bne\ta7,a6,0", print(bne, 0));
assert_eq!("beq\ta7,a6,0", print(beq, 0));
}
#[test]
fn test_small_program() {
/* Code for :
int a = 0;
int b = 5;
a = b;
a = a * b;
a = a + b;
b = a - b;
*/
assert_eq!("addi sp,sp,-32", print(decode(0xfe010113), 0));
assert_eq!("sd s0,24(sp)", print(decode(0x00813c23), 0));
assert_eq!("addi s0,sp,32", print(decode(0x02010413), 0));
assert_eq!("sw zero,-20(s0)", print(decode(0xfe042623), 0));
assert_eq!("addi a5,zero,5", print(decode(0x00500793), 0));
assert_eq!("sw a5,-24(s0)", print(decode(0xfef42423), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("sw a5,-20(s0)", print(decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print(decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("mulw a5,a4,a5", print(decode(0x02f707bb), 0));
assert_eq!("sw a5,-20(s0)", print(decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print(decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("addw a5,a4,a5", print(decode(0x00f707bb), 0));
assert_eq!("sw a5,-20(s0)", print(decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print(decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("subw a5,a4,a5", print(decode(0x40f707bb), 0));
assert_eq!("sw a5,-24(s0)", print(decode(0xfef42423), 0));
assert_eq!("addi a5,zero,0", print(decode(0x00000793), 0));
assert_eq!("addi a0,a5,0", print(decode(0x00078513), 0));
assert_eq!("ld s0,24(sp)", print(decode(0x01813403), 0));
assert_eq!("addi sp,sp,32", print(decode(0x02010113), 0));
assert_eq!("jalr zero,0(ra)", print(decode(0x00008067), 0));
}
#[test]
fn test_fibo() {
assert_eq!("jal zero,10504", print(decode(0x0500006f), 0x104b4));
assert_eq!("blt a4,a5,104b8", print(decode(0xfaf740e3), 0x10518));
}
#[test]
fn test_mul_prog() {
assert_eq!("addi sp,sp,-32", print(decode(0xfe010113), 0));
assert_eq!("sd s0,24(sp)", print(decode(0x00813c23), 0));
assert_eq!("addi s0,sp,32", print(decode(0x02010413), 0));
assert_eq!("addi a5,zero,5", print(decode(0x00500793), 0));
assert_eq!("sw a5,-20(s0)", print(decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print(decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("addi a5,a4,0", print(decode(0x00070793), 0));
assert_eq!("slliw a5,a5,0x2", print(decode(0x0027979b), 0));
assert_eq!("addw a5,a5,a4", print(decode(0x00e787bb), 0));
assert_eq!("sw a5,-24(s0)", print(decode(0xfef42423), 0));
assert_eq!("lw a5,-20(s0)", print(decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("mulw a5,a4,a5", print(decode(0x02f707bb), 0));
assert_eq!("sw a5,-28(s0)", print(decode(0xfef42223), 0));
assert_eq!("lw a5,-28(s0)", print(decode(0xfe442783), 0));
assert_eq!("addi a4,a5,0", print(decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print(decode(0xfe842783), 0));
assert_eq!("divw a5,a4,a5", print(decode(0x02f747bb), 0));
assert_eq!("sw a5,-20(s0)", print(decode(0xfef42623), 0));
assert_eq!("addi a5,zero,0", print(decode(0x00000793), 0));
assert_eq!("addi a0,a5,0", print(decode(0x00078513), 0));
assert_eq!("ld s0,24(sp)", print(decode(0x01813403), 0));
assert_eq!("addi sp,sp,32", print(decode(0x02010113), 0));
assert_eq!("jalr zero,0(ra)", print(decode(0x00008067), 0));
}
}

372
src/simulator/machine.rs
View File

@ -16,9 +16,8 @@ use std::{
fs::File
};
use crate::simulator::{
print,
error::MachineError,
decode::*,
instruction::{*, self},
interrupt::Interrupt,
global::*,
register::*
@ -197,10 +196,10 @@ impl Machine {
pub fn print_status(&self) {
println!("######### Machine status #########");
for i in (0..32).step_by(3) {
print!(">{0: <4} : {1:<16x} ", print::REG_X[i], self.int_reg.get_reg(i as u8));
print!(">{0: <4} : {1:<16x} ", print::REG_X[i+1], self.int_reg.get_reg((i+1) as u8));
print!(">{0: <4} : {1:<16x} ", instruction::REG_X[i], self.int_reg.get_reg(i as u8));
print!(">{0: <4} : {1:<16x} ", instruction::REG_X[i+1], self.int_reg.get_reg((i+1) as u8));
if i+2 < 32 {
print!(">{0: <4} : {1:<16x} ", print::REG_X[i+2], self.int_reg.get_reg((i+2) as u8));
print!(">{0: <4} : {1:<16x} ", instruction::REG_X[i+2], self.int_reg.get_reg((i+2) as u8));
}
println!();
}
@ -267,7 +266,7 @@ impl Machine {
let inst : Instruction = decode(val);
self.print_status();
println!("executing instruction : {:016x} at pc {:x}", val, self.pc);
println!("{}", print::print(decode(val), self.pc as i32));
println!("{}", instruction::print(decode(val), self.pc as i32));
let trace = Self::string_registers(self);
self.registers_trace.push_str(format!("{}\n", trace).as_str());
@ -302,28 +301,28 @@ impl Machine {
},
// Treatment for: BRANCH INSTRUCTIONS
RISCV_BR => self.branch_instruction(inst),
RISCV_BR => self.branch_instruction(inst),
// Treatment for: LOAD INSTRUCTIONS
RISCV_LD => self.load_instruction(inst),
RISCV_LD => self.load_instruction(inst),
// Treatment for: STORE INSTRUCTIONS
RISCV_ST => self.store_instruction(inst),
// Treatment for: OPI INSTRUCTIONS
RISCV_OPI => self.opi_instruction(inst),
RISCV_ST => self.store_instruction(inst),
// Treatment for: OP INSTRUCTIONS
RISCV_OP => self.op_instruction(inst),
RISCV_OP => self.op_instruction(inst),
// Treatment for: OPI INSTRUCTIONS
RISCV_OPI => self.opi_instruction(inst),
// Treatment for: OPW INSTRUCTIONS
RISCV_OPW => self.opw_instruction(inst),
// Treatment for OPIW INSTRUCTIONS
RISCV_OPIW => self.opiw_instruction(inst),
// Treatment for: OPW INSTRUCTIONS
RISCV_OPW => self.opw_instruction(inst),
RISCV_OPIW => self.opiw_instruction(inst),
// Treatment for: FLOATING POINT INSTRUCTIONS
RISCV_FP => self.fp_instruction(inst),
RISCV_FP => self.fp_instruction(inst),
// Treatment for: SYSTEM CALLS
RISCV_SYSTEM => self.raise_exception(ExceptionType::SyscallException, self.pc),
@ -342,7 +341,7 @@ impl Machine {
RISCV_BR_BGE => |a, b| a >= b,
RISCV_BR_BLTU => |a, b| a < b,
RISCV_BR_BGEU => |a, b| a >= b,
_ => unreachable!()
_ => Err(format!("Unreachable in branch_instruction match! Instruction was {:?}", inst))?
};
let rs1 = self.int_reg.get_reg(inst.rs1);
let rs2 = self.int_reg.get_reg(inst.rs2);
@ -360,11 +359,11 @@ impl Machine {
Ok(())
};
match inst.funct3 {
RISCV_LD_LB | RISCV_LD_LBU => set_reg(inst.rd, 1),
RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2),
RISCV_LD_LW | RISCV_LD_LWU => set_reg(inst.rd, 4),
RISCV_LD_LD => set_reg(inst.rd, 8),
_ => Err(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str())?
RISCV_LD_LB | RISCV_LD_LBU => set_reg(inst.rd, 1),
RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2),
RISCV_LD_LW | RISCV_LD_LWU => set_reg(inst.rd, 4),
RISCV_LD_LD => set_reg(inst.rd, 8),
_ => Err(format!("Unreachable in load_instruction match! Instruction was {:?}", inst))?
}
}
@ -383,7 +382,7 @@ impl Machine {
RISCV_ST_STH => store(2),
RISCV_ST_STW => store(4),
RISCV_ST_STD => store(8),
_ => Err(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str())?
_ => Err(format!("Unreachable in store_instruction match! Instruction was {:?}", inst))?
}
}
@ -397,18 +396,18 @@ impl Machine {
Ok(())
};
match inst.funct3 {
RISCV_OPI_ADDI => compute(&std::ops::Add::add, rs1, imm12),
RISCV_OPI_SLTI => compute(&|a, b| (a < b) as i64, rs1, imm12),
RISCV_OPI_XORI => compute(&core::ops::BitXor::bitxor, rs1, imm12),
RISCV_OPI_ORI => compute(&core::ops::BitOr::bitor, rs1, imm12),
RISCV_OPI_ANDI => compute(&core::ops::BitAnd::bitand, rs1, imm12),
RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, imm12),
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
} else {
compute(&core::ops::Shr::shr, rs1, shamt)
}
_ => Err(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value))?
RISCV_OPI_ADDI => compute(&std::ops::Add::add, rs1, imm12),
RISCV_OPI_SLTI => compute(&|a, b| (a < b) as i64, rs1, imm12),
RISCV_OPI_XORI => compute(&core::ops::BitXor::bitxor, rs1, imm12),
RISCV_OPI_ORI => compute(&core::ops::BitOr::bitor, rs1, imm12),
RISCV_OPI_ANDI => compute(&core::ops::BitAnd::bitand, rs1, imm12),
RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, imm12),
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
} else {
compute(&core::ops::Shr::shr, rs1, shamt)
}
_ => Err(format!("Unreachable in opi_instruction match! Instruction was {:?}", inst))?
}
}
@ -419,55 +418,55 @@ impl Machine {
let unsigned_reg2: u64;
if inst.funct7 == 1 {
match inst.funct3 {
RISCV_OP_M_MUL => {
long_result = (self.int_reg.get_reg(inst.rs1) * self.int_reg.get_reg(inst.rs2)) as i128;
self.int_reg.set_reg(inst.rd, (long_result & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULH => {
long_result = (self.int_reg.get_reg(inst.rs1) * self.int_reg.get_reg(inst.rs2)) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULHSU => {
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
long_result = (self.int_reg.get_reg(inst.rs1) as u64 * unsigned_reg2) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULHU => {
unsigned_reg1 = self.int_reg.get_reg(inst.rs1) as u64;
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64);
},
RISCV_OP_M_DIV => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) / self.int_reg.get_reg(inst.rs2)),
_ => panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n")
RISCV_OP_M_MUL => {
long_result = (self.int_reg.get_reg(inst.rs1) * self.int_reg.get_reg(inst.rs2)) as i128;
self.int_reg.set_reg(inst.rd, (long_result & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULH => {
long_result = (self.int_reg.get_reg(inst.rs1) * self.int_reg.get_reg(inst.rs2)) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULHSU => {
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
long_result = (self.int_reg.get_reg(inst.rs1) as u64 * unsigned_reg2) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64)
},
RISCV_OP_M_MULHU => {
unsigned_reg1 = self.int_reg.get_reg(inst.rs1) as u64;
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
self.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64);
},
RISCV_OP_M_DIV => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) / self.int_reg.get_reg(inst.rs2)),
_ => Err(format!("Unreachable in op_instruction match! Instruction was {:?}", inst))?
}
} else {
match inst.funct3 {
RISCV_OP_ADD => if inst.funct7 == RISCV_OP_ADD_ADD {
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) + self.int_reg.get_reg(inst.rs2))
} else {
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) - self.int_reg.get_reg(inst.rs2))
},
RISCV_OP_SLL => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) << (self.int_reg.get_reg(inst.rs2) & 0x3f)),
RISCV_OP_SLT => if self.int_reg.get_reg(inst.rs1) < self.int_reg.get_reg(inst.rs2) {
self.int_reg.set_reg(inst.rd, 1)
} else {
self.int_reg.set_reg(inst.rd, 0)
},
RISCV_OP_SLTU => {
unsigned_reg1 = self.int_reg.get_reg(inst.rs1) as u64;
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
if unsigned_reg1 < unsigned_reg2 {
self.int_reg.set_reg(inst.rd, 1)
} else {
self.int_reg.set_reg(inst.rd, 0)
}
},
RISCV_OP_XOR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) ^ self.int_reg.get_reg(inst.rs2)),
RISCV_OP_SR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> self.int_reg.get_reg(inst.rs2)), // RISCV_OP_SR_SRL inaccessible
RISCV_OP_OR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) | self.int_reg.get_reg(inst.rs2)),
RISCV_OP_AND => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) & self.int_reg.get_reg(inst.rs2)),
_ => panic!("RISCV_OP undefined case\n")
RISCV_OP_ADD => if inst.funct7 == RISCV_OP_ADD_ADD {
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) + self.int_reg.get_reg(inst.rs2))
} else {
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) - self.int_reg.get_reg(inst.rs2))
},
RISCV_OP_SLL => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) << (self.int_reg.get_reg(inst.rs2) & 0x3f)),
RISCV_OP_SLT => if self.int_reg.get_reg(inst.rs1) < self.int_reg.get_reg(inst.rs2) {
self.int_reg.set_reg(inst.rd, 1)
} else {
self.int_reg.set_reg(inst.rd, 0)
},
RISCV_OP_SLTU => {
unsigned_reg1 = self.int_reg.get_reg(inst.rs1) as u64;
unsigned_reg2 = self.int_reg.get_reg(inst.rs2) as u64;
if unsigned_reg1 < unsigned_reg2 {
self.int_reg.set_reg(inst.rd, 1)
} else {
self.int_reg.set_reg(inst.rd, 0)
}
},
RISCV_OP_XOR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) ^ self.int_reg.get_reg(inst.rs2)),
RISCV_OP_SR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> self.int_reg.get_reg(inst.rs2)), // RISCV_OP_SR_SRL inaccessible
RISCV_OP_OR => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) | self.int_reg.get_reg(inst.rs2)),
RISCV_OP_AND => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) & self.int_reg.get_reg(inst.rs2)),
_ => Err(format!("Unreachable in op_instruction match! Instruction was {:?}", inst))?
}
}
Ok(())
@ -479,8 +478,8 @@ impl Machine {
let result = match inst.funct3 {
RISCV_OPIW_ADDIW => local_data + inst.imm12_I_signed as i64,
RISCV_OPIW_SLLIW => local_data << inst.shamt,
RISCV_OPIW_SRW => (local_data >> inst.shamt) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.shamt as usize] as i64 } else { 1 },
_ => Err("In OPI switch case, this should never happen... Instr was {}\n")?,
RISCV_OPIW_SRW => (local_data >> inst.shamt) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.shamt as usize] as i64 } else { 1 },
_ => Err(format!("Unreachable in op_instruction match! Instruction was {:?}", inst))?
};
self.int_reg.set_reg(inst.rd, result);
Ok(())
@ -496,105 +495,142 @@ impl Machine {
// Match case for multiplication operations (in standard extension RV32M)
match inst.funct3 {
RISCV_OPW_M_MULW => self.int_reg.set_reg(inst.rd, local_data_a * local_data_b),
RISCV_OPW_M_DIVW => self.int_reg.set_reg(inst.rd, local_data_a / local_data_b),
RISCV_OPW_M_DIVUW => self.int_reg.set_reg(inst.rd, local_data_a_unsigned / local_data_b_unsigned),
RISCV_OPW_M_REMW => self.int_reg.set_reg(inst.rd, local_data_a % local_data_b),
RISCV_OPW_M_REMUW => self.int_reg.set_reg(inst.rd, local_data_a_unsigned % local_data_b_unsigned),
_ => panic!("this instruction ({}) doesn't exists", inst.value)
RISCV_OPW_M_MULW => self.int_reg.set_reg(inst.rd, local_data_a * local_data_b),
RISCV_OPW_M_DIVW => self.int_reg.set_reg(inst.rd, local_data_a / local_data_b),
RISCV_OPW_M_DIVUW => self.int_reg.set_reg(inst.rd, local_data_a_unsigned / local_data_b_unsigned),
RISCV_OPW_M_REMW => self.int_reg.set_reg(inst.rd, local_data_a % local_data_b),
RISCV_OPW_M_REMUW => self.int_reg.set_reg(inst.rd, local_data_a_unsigned % local_data_b_unsigned),
_ => Err(format!("Unreachable in opw_instruction match! Instruction was {:?}", inst))?
}
} else { // others rv64 OPW operations
let local_dataa = self.int_reg.get_reg(inst.rs1) & 0xffffffff;
let local_datab = self.int_reg.get_reg(inst.rs2) & 0xffffffff;
// Match case for base OP operation
match inst.funct3 {
RISCV_OPW_ADDSUBW => if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
self.int_reg.set_reg(inst.rd, local_dataa + local_datab);
} else { // SUBW
self.int_reg.set_reg(inst.rd, local_dataa - local_datab);
},
RISCV_OPW_SLLW => self.int_reg.set_reg(inst.rd, local_dataa << (local_datab & 0x1f)),
RISCV_OPW_SRW => if inst.funct7 == RISCV_OPW_SRW_SRLW {
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f) & self.shiftmask[32 + local_datab as usize] as i64)
} else { // SRAW
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f))
},
_ => panic!("this instruction ({}) doesn't exist", inst.value)
RISCV_OPW_ADDSUBW => if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
self.int_reg.set_reg(inst.rd, local_dataa + local_datab);
} else { // SUBW
self.int_reg.set_reg(inst.rd, local_dataa - local_datab);
},
RISCV_OPW_SLLW => self.int_reg.set_reg(inst.rd, local_dataa << (local_datab & 0x1f)),
RISCV_OPW_SRW => if inst.funct7 == RISCV_OPW_SRW_SRLW {
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f) & self.shiftmask[32 + local_datab as usize] as i64)
} else { // SRAW
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f))
},
_ => Err(format!("Unreachable in opw_instruction match! Instruction was {:?}", inst))?
}
}
Ok(())
}
/// Executes simple RISC-V floating point instructions on the machine
/// Executes simple RISC-V floating point instructions on the machine.
///
/// See Risc-V Spec v2.2 Chapter 8: “F” Standard Extension for Single-Precision Floating-Point, Version 2.0.
fn fp_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut set_reg = |operation: &dyn Fn (f32, f32) -> f32| {
let a = self.fp_reg.get_reg(inst.rs1);
let b = self.fp_reg.get_reg(inst.rs2);
self.fp_reg.set_reg(inst.rd, operation(a, b));
Ok(())
};
match inst.funct7 {
RISCV_FP_ADD => self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) + self.fp_reg.get_reg(inst.rs2)),
RISCV_FP_SUB => self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) - self.fp_reg.get_reg(inst.rs2)),
RISCV_FP_MUL => self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) * self.fp_reg.get_reg(inst.rs2)),
RISCV_FP_DIV => self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) / self.fp_reg.get_reg(inst.rs2)),
RISCV_FP_SQRT => self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1).sqrt()),
RISCV_FP_FSGN => {
let local_float = self.fp_reg.get_reg(inst.rs1);
match inst.funct3 {
RISCV_FP_FSGN_J => if self.fp_reg.get_reg(inst.rs2) < 0f32 {
self.fp_reg.set_reg(inst.rd, -local_float)
} else {
self.fp_reg.set_reg(inst.rd, local_float)
},
RISCV_FP_FSGN_JN => if self.fp_reg.get_reg(inst.rs2) < 0f32 {
self.fp_reg.set_reg(inst.rd, local_float)
} else {
self.fp_reg.set_reg(inst.rd, -local_float)
},
RISCV_FP_FSGN_JX => if (self.fp_reg.get_reg(inst.rs2) < 0.0 && self.fp_reg.get_reg(inst.rs1) >= 0.0) ||
(self.fp_reg.get_reg(inst.rs2) >= 0.0 && self.fp_reg.get_reg(inst.rs1) < 0.0) {
self.fp_reg.set_reg(inst.rd, -local_float)
} else {
self.fp_reg.set_reg(inst.rd, local_float)
},
_ => panic!("this instruction ({}) doesn't exists", inst.value)
}
RISCV_FP_ADD => set_reg(&core::ops::Add::add),
RISCV_FP_SUB => set_reg(&core::ops::Sub::sub),
RISCV_FP_MUL => set_reg(&core::ops::Mul::mul),
RISCV_FP_DIV => set_reg(&core::ops::Div::div),
RISCV_FP_SQRT => { self.fp_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1).sqrt()); Ok(()) },
RISCV_FP_FSGN => self.fp_fsgn_instruction(inst),
RISCV_FP_MINMAX => self.fp_minmax_instruction(inst),
RISCV_FP_FCVTW => self.fp_fcvtw_instruction(inst),
RISCV_FP_FCVTS => self.fp_fcvts_instruction(inst),
RISCV_FP_FMVW => self.fp_fmvw_instruction(inst),
RISCV_FP_FMVXFCLASS => self.fp_fmvxfclass_instruction(inst),
RISCV_FP_FCMP => self.fp_fcmp_instruction(inst),
_ => Err(format!("Unreachable in fp_instruction match! Instruction was {:?}", inst))?
}
}
/// Executes RISC-V sign-injection instruction on floating point values on the machine.
fn fp_fsgn_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let local_float = self.fp_reg.get_reg(inst.rs1);
match inst.funct3 {
RISCV_FP_FSGN_J => if self.fp_reg.get_reg(inst.rs2) < 0f32 {
self.fp_reg.set_reg(inst.rd, -local_float);
} else {
self.fp_reg.set_reg(inst.rd, local_float);
},
RISCV_FP_MINMAX => {
let r1 = self.fp_reg.get_reg(inst.rs1);
let r2 = self.fp_reg.get_reg(inst.rs2);
match inst.funct3 {
RISCV_FP_MINMAX_MIN => self.fp_reg.set_reg(inst.rd, if r1 < r2 {r1} else {r2}),
RISCV_FP_MINMAX_MAX => self.fp_reg.set_reg(inst.rd, if r1 > r2 {r1} else {r2}),
_ => panic!("this instruction ({}) doesn't exists", inst.value)
}
RISCV_FP_FSGN_JN => if self.fp_reg.get_reg(inst.rs2) < 0f32 {
self.fp_reg.set_reg(inst.rd, local_float);
} else {
self.fp_reg.set_reg(inst.rd, -local_float);
},
RISCV_FP_FCVTW => {
if inst.rs2 == RISCV_FP_FCVTW_W {
self.int_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) as i64)
} else {
self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) as u64) as i64)
}
RISCV_FP_FSGN_JX => if (self.fp_reg.get_reg(inst.rs2) < 0.0 && self.fp_reg.get_reg(inst.rs1) >= 0.0) ||
(self.fp_reg.get_reg(inst.rs2) >= 0.0 && self.fp_reg.get_reg(inst.rs1) < 0.0) {
self.fp_reg.set_reg(inst.rd, -local_float);
} else {
self.fp_reg.set_reg(inst.rd, local_float);
},
RISCV_FP_FCVTS => {
if inst.rs2 == RISCV_FP_FCVTS_W {
self.fp_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) as f32);
} else {
self.fp_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) as u32) as f32);
}
},
RISCV_FP_FMVW => self.fp_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) as f32),
RISCV_FP_FMVXFCLASS => {
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
self.int_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) as i64);
} else {
panic!("Fclass instruction is not handled in riscv simulator");
}
},
RISCV_FP_FCMP => {
match inst.funct3 {
RISCV_FP_FCMP_FEQ => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) == self.fp_reg.get_reg(inst.rs2)) as i64),
RISCV_FP_FCMP_FLT => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) < self.fp_reg.get_reg(inst.rs2)) as i64),
RISCV_FP_FCMP_FLE => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) <= self.fp_reg.get_reg(inst.rs2)) as i64),
_ => panic!("this instruction ({}) doesn't exists", inst.value)
}
},
_ => panic!("this instruction ({}) doesn't exists", inst.value)
_ => Err(format!("Unreachable in fp_fsgn_instruction! Instruction was {:?}", inst))?
}
Ok(())
}
/// Executes RISC-V min / max instruction on floating point values on the machine.
fn fp_minmax_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let r1 = self.fp_reg.get_reg(inst.rs1);
let r2 = self.fp_reg.get_reg(inst.rs2);
match inst.funct3 {
RISCV_FP_MINMAX_MIN => self.fp_reg.set_reg(inst.rd, if r1 < r2 {r1} else {r2}),
RISCV_FP_MINMAX_MAX => self.fp_reg.set_reg(inst.rd, if r1 > r2 {r1} else {r2}),
_ => Err(format!("Unreachable in fp_minmax_instruction! Instruction was {:?}", inst))?
};
Ok(())
}
/// Executes RISC-V floating-point to integer conversion instruction on the machine.
fn fp_fcvtw_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
if inst.rs2 == RISCV_FP_FCVTW_W {
self.int_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) as i64)
} else {
self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) as u64) as i64)
}
Ok(())
}
/// Executes RISC-V integer to floating-point conversion instruction on the machine.
fn fp_fcvts_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
if inst.rs2 == RISCV_FP_FCVTS_W {
self.fp_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) as f32);
} else {
self.fp_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) as u32) as f32);
}
Ok(())
}
/// Executes RISC-V move from int_reg to fp_reg instruction on the machine.
fn fp_fmvw_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
self.fp_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) as f32);
Ok(())
}
/// Executes RISC-V move from fp_reg to int_reg instruction on the machine.
fn fp_fmvxfclass_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
self.int_reg.set_reg(inst.rd, self.fp_reg.get_reg(inst.rs1) as i64);
Ok(())
} else {
Err(format!("Unreachable in fp_fmvxfclass_instruction! Instruction was {:?}", inst))?
}
}
/// Executes RISC-V floating point values comparaison instructions on the machine.
fn fp_fcmp_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
match inst.funct3 {
RISCV_FP_FCMP_FEQ => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) == self.fp_reg.get_reg(inst.rs2)) as i64),
RISCV_FP_FCMP_FLT => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) < self.fp_reg.get_reg(inst.rs2)) as i64),
RISCV_FP_FCMP_FLE => self.int_reg.set_reg(inst.rd, (self.fp_reg.get_reg(inst.rs1) <= self.fp_reg.get_reg(inst.rs2)) as i64),
_ => Err(format!("Unreachable in fp_fcmp_instruction match! Instruction was {:?}", inst))?
}
Ok(())
}

3
src/simulator/mod.rs
View File

@ -1,7 +1,6 @@
pub mod machine;
pub mod error;
pub mod decode;
pub mod print;
pub mod instruction;
pub mod mem_cmp;
pub mod loader;
pub mod interrupt;

414
src/simulator/print.rs
View File

@ -1,414 +0,0 @@
#![allow(dead_code)]
use super::decode::{Instruction};
use super::global::*;
const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"];
const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
// Register name mapping
pub const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"];
const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
"ft8", "ft9", "ft10", "ft11"];
pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let rd = ins.rd as usize;
let rs1 = ins.rs1 as usize;
let rs2 = ins.rs2 as usize;
let rs3 = ins.rs3 as usize;
match ins.opcode {
RISCV_OP => {
let name: &str;
if ins.funct7 == 1 { // Use mul array
name = NAMES_MUL[ins.funct3 as usize]
} else if ins.funct3 == RISCV_OP_ADD {
// Add or Sub
if ins.funct7 == RISCV_OP_ADD_ADD {
name = "add";
} else {
name = "sub";
}
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else {
name = NAMES_OP[ins.funct3 as usize];
}
format!("{}\t{},{},{}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
},
RISCV_OPI => {
// SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("srli\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
} else {
format!("srai\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
}
} else if ins.funct3 == RISCV_OPI_SLLI {
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt)
} else {
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
}
},
RISCV_LUI => {
format!("lui\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_AUIPC => {
format!("auipc\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_JAL => {
format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed))
},
RISCV_JALR => {
format!("jalr\t{},{:x}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
},
RISCV_BR => {
format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32))
},
RISCV_LD => {
format!("{}\t{},{}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
},
RISCV_ST => {
format!("{}\t{},{}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1])
},
RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srliw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else {
format!("{}\t{},{},0x{:x}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
}
},
RISCV_OPW => {
if ins.funct7 == 1 {
format!("{}w\t{},{},{}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else if ins.funct3 == RISCV_OP_ADD {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("subw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else {
format!("{}\t{},{},{}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
}
},
// RV32F Standard Extension
RISCV_FLW => {
format!("flw\t{},{},({})", REG_F[rd], ins.imm12_I_signed, REG_F[rs1])
},
RISCV_FSW => {
format!("fsw\t{},{},({})", REG_F[rs2], "OFFSET TODO", REG_F[rs1]) // TODO Offset in decode
},
RISCV_FMADD => {
format!("fmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FMSUB => {
format!("fmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FNMSUB => {
format!("fnmsub\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FNMADD => {
format!("fnmadd\t{}{}{}{}", REG_F[rd], REG_F[rs1], REG_F[rs2], REG_F[rs3])
},
RISCV_FP => {
match ins.funct7 {
RISCV_FP_ADD => {
format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_SUB => {
format!("{}\t{}{}{}", "fsub.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_MUL => {
format!("{}\t{}{}{}", "fmul.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_DIV => {
format!("{}\t{}{}{}", "fdiv.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_SQRT => {
format!("{}\t{}{}", "fsqrt.s", REG_F[rd], REG_F[rs1])
},
RISCV_FP_FSGN => {
match ins.funct3 {
RISCV_FP_FSGN_J => {
format!("{}\t{}{}{}", "fsgnj.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_FSGN_JN => {
format!("{}\t{}{}{}", "fsgnn.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
RISCV_FP_FSGN_JX => {
format!("{}\t{}{}{}", "fsgnx.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
},
_ => todo!("Unknown code")
}
},
RISCV_FP_MINMAX => {
if ins.funct3 == 0 {
format!("{}\t{}{}{}", "fmin.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else {
format!("{}\t{}{}{}", "fmax.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}
},
RISCV_FP_FCVTW => {
if rs2 == 0 {
format!("{}\t{}{}", "fcvt.w.s", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fcvt.wu.s", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FMVXFCLASS => {
if ins.funct3 == 0 {
format!("{}\t{}{}", "fmv.x.w", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fclass.s", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FCMP => {
if ins.funct3 == 0 {
format!("{}\t{}{}{}", "fle.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else if ins.funct3 == 1 {
format!("{}\t{}{}{}", "flt.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else {
format!("{}\t{}{}{}", "feq.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}
},
RISCV_FP_FCVTS => {
if rs2 == 0 {
format!("{}\t{}{}", "fcvt.s.w", REG_F[rd], REG_F[rs1])
} else {
format!("{}\t{}{}", "fcvt.s.wu", REG_F[rd], REG_F[rs1])
}
},
RISCV_FP_FMVW => {
format!("{}\t{}{}", "fmv.w.x", REG_F[rd], REG_F[rs1])
},
_ => todo!("Unknown code")
}
},
RISCV_SYSTEM => {
"ecall".to_string()
},
_ => todo!("{:x} opcode non géré pc : {:x}, value : {:x}", ins.opcode, pc, ins.value) // Change todo! to panic! in the future, I put todo! because there's a lot of opcode currently not implemented
}
}
#[cfg(test)]
mod test {
#![allow(clippy::unusual_byte_groupings)]
use crate::simulator::{decode, print};
#[test]
fn test_op() {
let sub = decode::decode(0b0100000_10000_10001_000_11100_0110011);
let add = decode::decode(0b0000000_10000_10001_000_11100_0110011);
let xor = decode::decode(0b0000000_10000_10001_100_11100_0110011);
let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
assert_eq!("sub\tt3,a7,a6", print::print(sub, 0));
assert_eq!("xor\tt3,a7,a6", print::print(xor, 0));
assert_eq!("srl\tt3,a7,a6", print::print(slr, 0));
assert_eq!("sra\tt3,a7,a6", print::print(sra, 0));
assert_eq!("add\tt3,a7,a6", print::print(add, 0));
}
#[test]
fn test_opi() {
let addi = decode::decode(0b0000000000_10001_000_11100_0010011);
let slli = decode::decode(0b0000000000_10001_001_11100_0010011);
let slti = decode::decode(0b0000000000_10001_010_11100_0010011);
let sltiu = decode::decode(0b0000000000_10001_011_11100_0010011);
let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
assert_eq!("andi\tt3,a7,0", print::print(andi, 0));
assert_eq!("addi\tt3,a7,0", print::print(addi, 0));
assert_eq!("slli\tt3,a7,0", print::print(slli, 0));
assert_eq!("slti\tt3,a7,0", print::print(slti, 0));
assert_eq!("sltiu\tt3,a7,0", print::print(sltiu, 0));
assert_eq!("xori\tt3,a7,0", print::print(xori, 0));
assert_eq!("ori\tt3,a7,0", print::print(ori, 0));
}
#[test]
fn test_lui() {
let lui = decode::decode(0b01110001000011111000_11100_0110111);
let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
assert_eq!("lui\tt3,710f8000", print::print(lui, 0));
assert_eq!("lui\tt3,f10f8000", print::print(lui_negatif, 0));
}
#[test]
fn test_ld() {
// imm rs1 f3 rd opcode
let lb = decode::decode(0b010111110000_10001_000_11100_0000011);
let lh = decode::decode(0b010111110000_10001_001_11100_0000011);
let lw = decode::decode(0b010111110000_10001_010_11100_0000011);
let lbu = decode::decode(0b010111110000_10001_100_11100_0000011);
let lhu = decode::decode(0b010111110000_10001_101_11100_0000011);
let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
assert_eq!("lb\tt3,1520(a7)", print::print(lb, 0));
assert_eq!("lh\tt3,1520(a7)", print::print(lh, 0));
assert_eq!("lw\tt3,1520(a7)", print::print(lw, 0));
assert_eq!("lbu\tt3,1520(a7)", print::print(lbu, 0));
assert_eq!("lhu\tt3,1520(a7)", print::print(lhu, 0));
assert_eq!("ld\tt3,1520(a7)", print::print(ld, 0));
assert_eq!("lwu\tt3,1520(a7)", print::print(lwu, 0));
}
#[test]
fn test_opw() {
let addw: decode::Instruction = decode::decode(0b0000000_10000_10001_000_11100_0111011);
let sllw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0111011);
let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
assert_eq!("addw\tt3,a7,a6", print::print(addw, 0));
assert_eq!("sllw\tt3,a7,a6", print::print(sllw, 0));
assert_eq!("srlw\tt3,a7,a6", print::print(srlw, 0));
assert_eq!("sraw\tt3,a7,a6", print::print(sraw, 0));
}
#[test]
fn test_opwi() {
let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
assert_eq!("addiw\tt3,a7,0x0", print::print(addiw, 0));
assert_eq!("slliw\tt3,a7,0x10", print::print(slliw, 0));
assert_eq!("srai\tt3,a7,17", print::print(srai, 0));
}
#[test]
fn test_br() {
let beq: decode::Instruction = decode::decode(0b0000000_10000_10001_000_00000_1100011);
let bne: decode::Instruction = decode::decode(0b0000000_10000_10001_001_00000_1100011);
let blt: decode::Instruction = decode::decode(0b0000000_10000_10001_100_00000_1100011);
let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
let bge2: decode::Instruction = decode::decode(0x00f75863);
let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
assert_eq!("blt\ta7,a6,0", print::print(blt, 0));
assert_eq!("bge\ta7,a6,0", print::print(bge, 0));
assert_eq!("bge\ta4,a5,104d4", print::print(bge2, 0x104c4));
assert_eq!("bltu\ta7,a6,0", print::print(bltu, 0));
assert_eq!("bgeu\ta7,a6,0", print::print(bgeu, 0));
assert_eq!("bne\ta7,a6,0", print::print(bne, 0));
assert_eq!("beq\ta7,a6,0", print::print(beq, 0));
}
#[test]
fn test_small_program() {
/* Code for :
int a = 0;
int b = 5;
a = b;
a = a * b;
a = a + b;
b = a - b;
*/
assert_eq!("addi sp,sp,-32", print::print(decode::decode(0xfe010113), 0));
assert_eq!("sd s0,24(sp)", print::print(decode::decode(0x00813c23), 0));
assert_eq!("addi s0,sp,32", print::print(decode::decode(0x02010413), 0));
assert_eq!("sw zero,-20(s0)", print::print(decode::decode(0xfe042623), 0));
assert_eq!("addi a5,zero,5", print::print(decode::decode(0x00500793), 0));
assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("addw a5,a4,a5", print::print(decode::decode(0x00f707bb), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("subw a5,a4,a5", print::print(decode::decode(0x40f707bb), 0));
assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
assert_eq!("addi a5,zero,0", print::print(decode::decode(0x00000793), 0));
assert_eq!("addi a0,a5,0", print::print(decode::decode(0x00078513), 0));
assert_eq!("ld s0,24(sp)", print::print(decode::decode(0x01813403), 0));
assert_eq!("addi sp,sp,32", print::print(decode::decode(0x02010113), 0));
assert_eq!("jalr zero,0(ra)", print::print(decode::decode(0x00008067), 0));
}
#[test]
fn test_fibo() {
assert_eq!("jal zero,10504", print::print(decode::decode(0x0500006f), 0x104b4));
assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518));
}
#[test]
fn test_mul_prog() {
assert_eq!("addi sp,sp,-32", print::print(decode::decode(0xfe010113), 0));
assert_eq!("sd s0,24(sp)", print::print(decode::decode(0x00813c23), 0));
assert_eq!("addi s0,sp,32", print::print(decode::decode(0x02010413), 0));
assert_eq!("addi a5,zero,5", print::print(decode::decode(0x00500793), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("addi a5,a4,0", print::print(decode::decode(0x00070793), 0));
assert_eq!("slliw a5,a5,0x2", print::print(decode::decode(0x0027979b), 0));
assert_eq!("addw a5,a5,a4", print::print(decode::decode(0x00e787bb), 0));
assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));
assert_eq!("sw a5,-28(s0)", print::print(decode::decode(0xfef42223), 0));
assert_eq!("lw a5,-28(s0)", print::print(decode::decode(0xfe442783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("divw a5,a4,a5", print::print(decode::decode(0x02f747bb), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("addi a5,zero,0", print::print(decode::decode(0x00000793), 0));
assert_eq!("addi a0,a5,0", print::print(decode::decode(0x00078513), 0));
assert_eq!("ld s0,24(sp)", print::print(decode::decode(0x01813403), 0));
assert_eq!("addi sp,sp,32", print::print(decode::decode(0x02010113), 0));
assert_eq!("jalr zero,0(ra)", print::print(decode::decode(0x00008067), 0));
}
}

8
src/simulator/register.rs
View File

@ -6,6 +6,14 @@
use crate::simulator::machine::{NUM_FP_REGS, NUM_INT_REGS};
use std::ops::{Add, Sub};
/// Forcing the Register struct's generic type into having the following Traits
///
/// - Add
/// - Sub
/// - PartialEq
/// - Copy
///
/// Generally speaking, only numbers have the combinaison of these traits.
pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
impl RegisterNum for i64 {}