diff --git a/src/machine.rs b/src/machine.rs
index 2bb70f7..788db98 100644
--- a/src/machine.rs
+++ b/src/machine.rs
@@ -31,6 +31,15 @@ impl Machine {
 	
 		let mut unsigned_reg1 : u64 = 0;
 		let mut unsigned_reg2 : u64 = 0;
+		let mut long_result : i128 = 0;
+		 
+		 /*__int128 longResult;
+  		int32_t localDataa, localDatab;
+  		int64_t localLongResult;
+  		uint32_t localDataaUnsigned, localDatabUnsigned;
+  		int32_t localResult;
+  		float localFloat;
+  		uint64_t value;*/
 	
 		if machine.instructions.len() <= machine.pc as usize {
 			println!("ERROR : number max of instructions rushed");
@@ -79,49 +88,84 @@ impl Machine {
 			},
 			
 			RISCV_OP => {
-				match inst.funct3 {
-					RISCV_OP_ADD => {
-					// RISCV_OP_ADD_ADD inaccessible
-						/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
-						//}
-					},
-					RISCV_OP_SLL => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
-					},
-					RISCV_OP_SLT => {
-						if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
-						machine.int_reg[inst.rd as usize] = 1;
-						} else {
-						machine.int_reg[inst.rd as usize] = 0;
+				if(inst.funct7 == 1){
+					match inst.funct3 {
+						RISCV_OP_M_MUL => {
+							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
+							machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32;
+						},
+						RISCV_OP_M_MULH => {
+							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
+												
+						},
+						RISCV_OP_M_MULHSU => {
+							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
+            						long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
+            						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u32;
+						},
+						// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
+						/*
+						* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
+						* WHAT DA HECK
+						*/
+						RISCV_OP_M_MULHU => {
+							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
+            						unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
+            						long_result   = (unsigned_reg1 * unsigned_reg2) as i128;
+	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u32;
+						},
+						RISCV_OP_M_DIV => {
+							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);
 						}
-					},
-					RISCV_OP_SLTU => {
-						unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
-						unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
-						if unsigned_reg1 < unsigned_reg2 {
-							machine.int_reg[inst.rd as usize] = 1;
-						} else {
-							machine.int_reg[inst.rd as usize] = 0;
+						_ => {
+							println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
 						}
-					},
-					RISCV_OP_XOR => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
-					},
-					RISCV_OP_SR => {
-					// RISCV_OP_SR_SRL inaccessible
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
-					},
-					RISCV_OP_OR => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
-					},
-					RISCV_OP_AND => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
-					},
-					_ => {
-						println!("RISCV_OP undefined case\n");
 					}
+				} else {
+					match inst.funct3 {
+						RISCV_OP_ADD => {
+						// RISCV_OP_ADD_ADD inaccessible
+							/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
+								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
+							//}
+						},
+						RISCV_OP_SLL => {
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
+						},
+						RISCV_OP_SLT => {
+							if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
+							machine.int_reg[inst.rd as usize] = 1;
+							} else {
+							machine.int_reg[inst.rd as usize] = 0;
+							}
+						},
+						RISCV_OP_SLTU => {
+							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
+							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
+							if unsigned_reg1 < unsigned_reg2 {
+								machine.int_reg[inst.rd as usize] = 1;
+							} else {
+								machine.int_reg[inst.rd as usize] = 0;
+							}
+						},
+						RISCV_OP_XOR => {
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
+						},
+						RISCV_OP_SR => {
+						// RISCV_OP_SR_SRL inaccessible
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
+						},
+						RISCV_OP_OR => {
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
+						},
+						RISCV_OP_AND => {
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
+						},
+						_ => {
+							println!("RISCV_OP undefined case\n");
+						}
+					}//LA
 				}
 			}
 			_ => { println!("{} opcode non géré", inst.opcode)},