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♻️ Machine::write_memory is now indeed a self method

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François Autin 2023-03-24 18:36:02 +01:00
parent b33c31ef38
commit a2d5b22774
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 8 additions and 8 deletions
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16
src/simulator/machine.rs
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@ -128,13 +128,13 @@ impl Machine {
/// - **size** the number of bytes to write (1, 2, 4 or 8)
/// - **address** the address to write to
/// - **value** data to be written
pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) {
pub fn write_memory(&mut self, size: i32, address: usize, value: u64) {
if ![1, 2, 4, 8].contains(&size) {
panic!("ERROR write_memory: WRONG `size` PARAMETER ({size}), must be 1, 2, 4 or 8")
}
for i in 0..size as usize {
let inv_i = size as usize - i - 1;
machine.main_memory[address + i] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8;
self.main_memory[address + i] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8;
}
}
@ -352,10 +352,10 @@ impl Machine {
/// Executes RISC-V Store Instructions on the machine
fn store_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
match inst.funct3 {
RISCV_ST_STB => Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STH => Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STW => Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STD => Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STB => machine.write_memory(1, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STH => machine.write_memory(2, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STW => machine.write_memory(4, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
RISCV_ST_STD => machine.write_memory(8, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64),
_ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value)
}
Ok(())
@ -659,10 +659,10 @@ mod test {
#[test]
fn test_write_memory() {
let mut m = Machine::init_machine();
Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
m.write_memory(2, 6, (43 << 8) + 150);
assert_eq!(43, m.main_memory[6]);
assert_eq!(150, m.main_memory[7]);
Machine::write_memory(&mut m, 4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150);
m.write_memory(4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150);
assert_eq!(52, m.main_memory[8]);
assert_eq!(20, m.main_memory[9]);
assert_eq!(43, m.main_memory[10]);