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♻️ Simplified OPI

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This commit is contained in:
François Autin 2023-03-27 11:22:53 +02:00
parent a8bbc13142
commit 939e23883e
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 21 additions and 15 deletions
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36
src/simulator/machine.rs
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@ -13,7 +13,7 @@
use std::{ use std::{
io::Write, io::Write,
fs::File fs::File, ops::Add
}; };
use crate::simulator::{ use crate::simulator::{
print, print,
@ -381,21 +381,27 @@ impl Machine {
/// Executes RISC-V Integer Register-Immediate Instructions on the machine /// Executes RISC-V Integer Register-Immediate Instructions on the machine
fn opi_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> { fn opi_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut compute = |operation: &dyn Fn (i64, i64) -> i64| {
self.int_reg.set_reg(inst.rd, operation(self.int_reg.get_reg(inst.rs1), inst.imm12_I_signed as i64));
Ok(())
};
match inst.funct3 { match inst.funct3 {
RISCV_OPI_ADDI => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64), RISCV_OPI_ADDI => compute(&std::ops::Add::add),
RISCV_OPI_SLTI => self.int_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) < inst.imm12_I_signed as i64) as i64), RISCV_OPI_SLTI => compute(&|a, b| { (a < b) as i64 }),
RISCV_OPI_XORI => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) ^ inst.imm12_I_signed as i64), RISCV_OPI_XORI => compute(&|a, b| { a ^ b }),
RISCV_OPI_ORI => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) | inst.imm12_I_signed as i64), RISCV_OPI_ORI => compute(&|a, b| { a | b }),
RISCV_OPI_ANDI => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) & inst.imm12_I_signed as i64), RISCV_OPI_ANDI => compute(&|a, b| { a & b }),
RISCV_OPI_SLLI => self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) << inst.shamt), RISCV_OPI_SLLI => compute(&|a, b| { a << b }),
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { RISCV_OPI_SRI => {
self.int_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) >> inst.shamt) & self.shiftmask[inst.shamt as usize] as i64); if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
} else { // SRAI self.int_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) >> inst.shamt) & self.shiftmask[inst.shamt as usize] as i64)
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> inst.shamt); } else { // SRAI
}, self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> inst.shamt)
_ => panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value) }
Ok(())
}
_ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str()))
} }
Ok(())
} }
/// Executes simple RISC-V mathematical operations on the machine /// Executes simple RISC-V mathematical operations on the machine
@ -517,7 +523,7 @@ impl Machine {
} else { // SRAW } else { // SRAW
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f)) self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f))
}, },
_ => panic!("this instruction ({}) doesn't exists", inst.value) _ => panic!("this instruction ({}) doesn't exist", inst.value)
} }
} }
Ok(()) Ok(())