diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index f8d3aed..dbd18bb 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -185,11 +185,11 @@ impl Machine {
 				machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
 			},
 			RISCV_AUIPC => {
-				machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
+				machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64);
 			},
 			RISCV_JAL => {
 				machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
-				machine.pc += inst.imm21_1_signed as u64 - 4;
+				machine.pc += inst.imm21_1_signed as u64 - 8;
 			},
 			RISCV_JALR => {
 				let tmp = machine.pc;
@@ -203,32 +203,32 @@ impl Machine {
 				match inst.funct3 {
 					RISCV_BR_BEQ => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					RISCV_BR_BNE => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					RISCV_BR_BLT => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					RISCV_BR_BGE => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					RISCV_BR_BLTU => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					RISCV_BR_BGEU => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 4;
+							machine.pc += inst.imm13_signed as u64 - 8;
 						}
 					},
 					_ => {