♻️ Documentation updates and fn renaming
This commit is contained in:
François Autin
parent
45a2ee952c
commit
8629d859e4
@ -1,34 +1,46 @@
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//! # Instruction
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//!
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//! This module describes the internal representation of an
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//!
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//! This module describes the internal representation of a RISC-V Instruction,
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//! its constructor from raw data, and a debug print method.
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#![allow(clippy::missing_docs_in_private_items, non_snake_case)]
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use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations voulues
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use super::global::*;
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/// OP instruction name mapping
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const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
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/// OPI instruction name mapping
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const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
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const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"];
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const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
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const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
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const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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/// OPW instruction name mapping
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const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
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/// OPIW instruction name mapping
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const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
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/// MUL instruction name mapping
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const NAMES_MUL: [&str; 8] = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"];
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/// BR instruction name mapping
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const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
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/// ST instruction name mapping
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const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
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/// LD instruction name mapping
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const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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// Register name mapping
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/// Integer register name mapping
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pub const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
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"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"];
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/// Floating-point register name mapping
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const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
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"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
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"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
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"ft8", "ft9", "ft10", "ft11"];
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/// RISC-V Instruction
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#[derive(Debug)]
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pub struct Instruction {
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/// Original value used to construct self
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pub value : u64,
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pub opcode : u8,
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@ -58,37 +70,36 @@ pub struct Instruction {
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impl Instruction {
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pub fn new(val : u64) -> Self {
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/// Construct a new instruction from a big endian raw binary instruction
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pub fn new(value : u64) -> Self {
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let value = val;
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let opcode = (val & 0x7f) as u8;
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let rs1 = ((val >> 15) & 0x1f) as u8;
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let rs2 = ((val >> 20) & 0x1f) as u8;
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let rs3 = ((val >> 27) & 0x1f) as u8;
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let rd = ((val >> 7) & 0x1f) as u8;
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let funct7 = ((val >> 25) & 0x7f) as u8;
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let opcode = (value & 0x7f) as u8;
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let rs1 = ((value >> 15) & 0x1f) as u8;
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let rs2 = ((value >> 20) & 0x1f) as u8;
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let rs3 = ((value >> 27) & 0x1f) as u8;
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let rd = ((value >> 7) & 0x1f) as u8;
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let funct7 = ((value >> 25) & 0x7f) as u8;
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let funct7_smaller = funct7 & 0x3e;
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let funct3 = ((val >> 12) & 0x7) as u8;
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let imm12_I = ((val >> 20) & 0xfff) as u16;
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let imm12_S = (((val >> 20) & 0xfe0) + ((val >> 7) & 0x1f)) as u16;
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let funct3 = ((value >> 12) & 0x7) as u8;
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let imm12_I = ((value >> 20) & 0xfff) as u16;
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let imm12_S = (((value >> 20) & 0xfe0) + ((value >> 7) & 0x1f)) as u16;
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let imm12_I_signed = if imm12_I >= 2048 { (Wrapping(imm12_I) - Wrapping(4096)).0 } else { imm12_I } as i16;
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let imm12_S_signed = if imm12_S >= 2048 { (Wrapping(imm12_S) - Wrapping(4096)).0 } else { imm12_S } as i16;
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let imm13 = (((val >> 19) & 0x1000) + ((val >> 20) & 0x7e0) +
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((val >> 7) & 0x1e) + ((val << 4) & 0x800)) as i16;
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let imm13 = (((value >> 19) & 0x1000) + ((value >> 20) & 0x7e0) +
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((value >> 7) & 0x1e) + ((value << 4) & 0x800)) as i16;
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let imm13_signed = if imm13 >= 4096 { imm13 - 8192 } else { imm13 };
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let imm31_12 = (val & 0xfffff000) as u32;
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let imm31_12 = (value & 0xfffff000) as u32;
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let imm31_12_signed = imm31_12 as i32;
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let imm21_1 = ((val & 0xff000) + ((val >> 9) & 0x800) +
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((val >> 20) & 0x7fe) + ((val >> 11) & 0x100000)) as u32;
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let imm21_1 = ((value & 0xff000) + ((value >> 9) & 0x800) +
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((value >> 20) & 0x7fe) + ((value >> 11) & 0x100000)) as u32;
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let imm21_1_signed = if imm21_1 >= 1048576 { (Wrapping(imm21_1) - Wrapping(2097152)).0 } else { imm21_1 } as i32;
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let shamt = ((val >> 20) & 0x3f) as u8;
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let shamt = ((value >> 20) & 0x3f) as u8;
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Instruction {
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value,
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@ -123,7 +134,16 @@ impl Instruction {
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}
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pub fn print_instruction_debug(ins: &Instruction, pc: i32) -> String { //TODO pc should be u64
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/// Converts an Instruction to a prettified debug String
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///
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/// ### Usage
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///
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/// ```
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/// let m = Machine::new();
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/// let i = Instruction::new(inst);
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/// println!("{}", instruction_debug(i, m.pc));
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/// ```
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pub fn instruction_debug(ins: &Instruction, pc: i32) -> String {
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let rd = ins.rd as usize;
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let rs1 = ins.rs1 as usize;
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let rs2 = ins.rs2 as usize;
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@ -335,11 +355,11 @@ mod test {
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let slr = Instruction::new(0b0000000_10000_10001_101_11100_0110011);
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let sra = Instruction::new(0b0100000_10000_10001_101_11100_0110011);
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assert_eq!("sub\tt3,a7,a6", print_instruction_debug(&sub, 0));
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assert_eq!("xor\tt3,a7,a6", print_instruction_debug(&xor, 0));
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assert_eq!("srl\tt3,a7,a6", print_instruction_debug(&slr, 0));
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assert_eq!("sra\tt3,a7,a6", print_instruction_debug(&sra, 0));
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assert_eq!("add\tt3,a7,a6", print_instruction_debug(&add, 0));
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assert_eq!("sub\tt3,a7,a6", instruction_debug(&sub, 0));
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assert_eq!("xor\tt3,a7,a6", instruction_debug(&xor, 0));
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assert_eq!("srl\tt3,a7,a6", instruction_debug(&slr, 0));
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assert_eq!("sra\tt3,a7,a6", instruction_debug(&sra, 0));
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assert_eq!("add\tt3,a7,a6", instruction_debug(&add, 0));
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}
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@ -352,21 +372,21 @@ mod test {
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let xori = Instruction::new(0b_0000000000010001_100_11100_0010011);
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let ori = Instruction::new(0b00000000000_10001_110_11100_0010011);
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let andi = Instruction::new(0b000000000000_10001_111_11100_0010011);
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assert_eq!("andi\tt3,a7,0", print_instruction_debug(&andi, 0));
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assert_eq!("addi\tt3,a7,0", print_instruction_debug(&addi, 0));
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assert_eq!("slli\tt3,a7,0", print_instruction_debug(&slli, 0));
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assert_eq!("slti\tt3,a7,0", print_instruction_debug(&slti, 0));
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assert_eq!("sltiu\tt3,a7,0", print_instruction_debug(&sltiu, 0));
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assert_eq!("xori\tt3,a7,0", print_instruction_debug(&xori, 0));
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assert_eq!("ori\tt3,a7,0", print_instruction_debug(&ori, 0));
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assert_eq!("andi\tt3,a7,0", instruction_debug(&andi, 0));
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assert_eq!("addi\tt3,a7,0", instruction_debug(&addi, 0));
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assert_eq!("slli\tt3,a7,0", instruction_debug(&slli, 0));
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assert_eq!("slti\tt3,a7,0", instruction_debug(&slti, 0));
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assert_eq!("sltiu\tt3,a7,0", instruction_debug(&sltiu, 0));
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assert_eq!("xori\tt3,a7,0", instruction_debug(&xori, 0));
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assert_eq!("ori\tt3,a7,0", instruction_debug(&ori, 0));
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}
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#[test]
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fn test_lui() {
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let lui = Instruction::new(0b01110001000011111000_11100_0110111);
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let lui_negatif = Instruction::new(0b11110001000011111000_11100_0110111);
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assert_eq!("lui\tt3,710f8000", print_instruction_debug(&lui, 0));
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assert_eq!("lui\tt3,f10f8000", print_instruction_debug(&lui_negatif, 0));
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assert_eq!("lui\tt3,710f8000", instruction_debug(&lui, 0));
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assert_eq!("lui\tt3,f10f8000", instruction_debug(&lui_negatif, 0));
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}
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#[test]
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@ -380,13 +400,13 @@ mod test {
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let ld = Instruction::new(0b010111110000_10001_011_11100_0000011);
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let lwu = Instruction::new(0b010111110000_10001_110_11100_0000011);
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assert_eq!("lb\tt3,1520(a7)", print_instruction_debug(&lb, 0));
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assert_eq!("lh\tt3,1520(a7)", print_instruction_debug(&lh, 0));
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assert_eq!("lw\tt3,1520(a7)", print_instruction_debug(&lw, 0));
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assert_eq!("lbu\tt3,1520(a7)", print_instruction_debug(&lbu, 0));
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assert_eq!("lhu\tt3,1520(a7)", print_instruction_debug(&lhu, 0));
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assert_eq!("ld\tt3,1520(a7)", print_instruction_debug(&ld, 0));
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assert_eq!("lwu\tt3,1520(a7)", print_instruction_debug(&lwu, 0));
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assert_eq!("lb\tt3,1520(a7)", instruction_debug(&lb, 0));
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assert_eq!("lh\tt3,1520(a7)", instruction_debug(&lh, 0));
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assert_eq!("lw\tt3,1520(a7)", instruction_debug(&lw, 0));
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assert_eq!("lbu\tt3,1520(a7)", instruction_debug(&lbu, 0));
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assert_eq!("lhu\tt3,1520(a7)", instruction_debug(&lhu, 0));
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assert_eq!("ld\tt3,1520(a7)", instruction_debug(&ld, 0));
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assert_eq!("lwu\tt3,1520(a7)", instruction_debug(&lwu, 0));
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}
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#[test]
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@ -396,10 +416,10 @@ mod test {
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let srlw: Instruction = Instruction::new(0b0000000_10000_10001_101_11100_0111011);
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let sraw: Instruction = Instruction::new(0b0100000_10000_10001_101_11100_0111011);
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assert_eq!("addw\tt3,a7,a6", print_instruction_debug(&addw, 0));
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assert_eq!("sllw\tt3,a7,a6", print_instruction_debug(&sllw, 0));
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assert_eq!("srlw\tt3,a7,a6", print_instruction_debug(&srlw, 0));
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assert_eq!("sraw\tt3,a7,a6", print_instruction_debug(&sraw, 0));
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assert_eq!("addw\tt3,a7,a6", instruction_debug(&addw, 0));
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assert_eq!("sllw\tt3,a7,a6", instruction_debug(&sllw, 0));
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assert_eq!("srlw\tt3,a7,a6", instruction_debug(&srlw, 0));
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assert_eq!("sraw\tt3,a7,a6", instruction_debug(&sraw, 0));
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}
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#[test]
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@ -407,9 +427,9 @@ mod test {
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let addiw: Instruction =Instruction::new(0b000000000000_10001_000_11100_0011011);
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let slliw: Instruction = Instruction::new(0b0000000_10000_10001_001_11100_0011011);
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let srai: Instruction = Instruction::new(0b010000010001_10001_101_11100_0010011);
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assert_eq!("addiw\tt3,a7,0x0", print_instruction_debug(&addiw, 0));
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assert_eq!("slliw\tt3,a7,0x10", print_instruction_debug(&slliw, 0));
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assert_eq!("srai\tt3,a7,17", print_instruction_debug(&srai, 0));
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assert_eq!("addiw\tt3,a7,0x0", instruction_debug(&addiw, 0));
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assert_eq!("slliw\tt3,a7,0x10", instruction_debug(&slliw, 0));
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assert_eq!("srai\tt3,a7,17", instruction_debug(&srai, 0));
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}
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@ -422,13 +442,13 @@ mod test {
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let bge2: Instruction = Instruction::new(0x00f75863);
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let bltu: Instruction = Instruction::new(0b0000000_10000_10001_110_00000_1100011);
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let bgeu: Instruction = Instruction::new(0b0000000_10000_10001_111_00000_1100011);
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assert_eq!("blt\ta7,a6,0", print_instruction_debug(&blt, 0));
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assert_eq!("bge\ta7,a6,0", print_instruction_debug(&bge, 0));
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assert_eq!("bge\ta4,a5,104d4", print_instruction_debug(&bge2, 0x104c4));
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assert_eq!("bltu\ta7,a6,0", print_instruction_debug(&bltu, 0));
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assert_eq!("bgeu\ta7,a6,0", print_instruction_debug(&bgeu, 0));
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assert_eq!("bne\ta7,a6,0", print_instruction_debug(&bne, 0));
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assert_eq!("beq\ta7,a6,0", print_instruction_debug(&beq, 0));
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assert_eq!("blt\ta7,a6,0", instruction_debug(&blt, 0));
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assert_eq!("bge\ta7,a6,0", instruction_debug(&bge, 0));
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assert_eq!("bge\ta4,a5,104d4", instruction_debug(&bge2, 0x104c4));
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assert_eq!("bltu\ta7,a6,0", instruction_debug(&bltu, 0));
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assert_eq!("bgeu\ta7,a6,0", instruction_debug(&bgeu, 0));
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assert_eq!("bne\ta7,a6,0", instruction_debug(&bne, 0));
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assert_eq!("beq\ta7,a6,0", instruction_debug(&beq, 0));
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}
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#[test]
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@ -441,72 +461,72 @@ mod test {
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a = a + b;
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b = a - b;
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*/
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assert_eq!("addi sp,sp,-32", print_instruction_debug(&Instruction::new(0xfe010113), 0));
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assert_eq!("sd s0,24(sp)", print_instruction_debug(&Instruction::new(0x00813c23), 0));
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assert_eq!("addi s0,sp,32", print_instruction_debug(&Instruction::new(0x02010413), 0));
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assert_eq!("sw zero,-20(s0)", print_instruction_debug(&Instruction::new(0xfe042623), 0));
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assert_eq!("addi a5,zero,5", print_instruction_debug(&Instruction::new(0x00500793), 0));
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assert_eq!("sw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfef42423), 0));
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assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
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assert_eq!("sw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfef42623), 0));
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assert_eq!("lw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfec42783), 0));
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assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
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assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
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assert_eq!("mulw a5,a4,a5", print_instruction_debug(&Instruction::new(0x02f707bb), 0));
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assert_eq!("sw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfef42623), 0));
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assert_eq!("lw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfec42783), 0));
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assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
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assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
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assert_eq!("addw a5,a4,a5", print_instruction_debug(&Instruction::new(0x00f707bb), 0));
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assert_eq!("sw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfef42623), 0));
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assert_eq!("lw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfec42783), 0));
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assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
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assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
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assert_eq!("subw a5,a4,a5", print_instruction_debug(&Instruction::new(0x40f707bb), 0));
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assert_eq!("sw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfef42423), 0));
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assert_eq!("addi a5,zero,0", print_instruction_debug(&Instruction::new(0x00000793), 0));
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assert_eq!("addi a0,a5,0", print_instruction_debug(&Instruction::new(0x00078513), 0));
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assert_eq!("ld s0,24(sp)", print_instruction_debug(&Instruction::new(0x01813403), 0));
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assert_eq!("addi sp,sp,32", print_instruction_debug(&Instruction::new(0x02010113), 0));
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assert_eq!("jalr zero,0(ra)", print_instruction_debug(&Instruction::new(0x00008067), 0));
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assert_eq!("addi sp,sp,-32", instruction_debug(&Instruction::new(0xfe010113), 0));
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assert_eq!("sd s0,24(sp)", instruction_debug(&Instruction::new(0x00813c23), 0));
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assert_eq!("addi s0,sp,32", instruction_debug(&Instruction::new(0x02010413), 0));
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assert_eq!("sw zero,-20(s0)", instruction_debug(&Instruction::new(0xfe042623), 0));
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assert_eq!("addi a5,zero,5", instruction_debug(&Instruction::new(0x00500793), 0));
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assert_eq!("sw a5,-24(s0)", instruction_debug(&Instruction::new(0xfef42423), 0));
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assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
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assert_eq!("sw a5,-20(s0)", instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("lw a5,-20(s0)", instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("mulw a5,a4,a5", instruction_debug(&Instruction::new(0x02f707bb), 0));
|
||||
assert_eq!("sw a5,-20(s0)", instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("lw a5,-20(s0)", instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("addw a5,a4,a5", instruction_debug(&Instruction::new(0x00f707bb), 0));
|
||||
assert_eq!("sw a5,-20(s0)", instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("lw a5,-20(s0)", instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("subw a5,a4,a5", instruction_debug(&Instruction::new(0x40f707bb), 0));
|
||||
assert_eq!("sw a5,-24(s0)", instruction_debug(&Instruction::new(0xfef42423), 0));
|
||||
assert_eq!("addi a5,zero,0", instruction_debug(&Instruction::new(0x00000793), 0));
|
||||
assert_eq!("addi a0,a5,0", instruction_debug(&Instruction::new(0x00078513), 0));
|
||||
assert_eq!("ld s0,24(sp)", instruction_debug(&Instruction::new(0x01813403), 0));
|
||||
assert_eq!("addi sp,sp,32", instruction_debug(&Instruction::new(0x02010113), 0));
|
||||
assert_eq!("jalr zero,0(ra)", instruction_debug(&Instruction::new(0x00008067), 0));
|
||||
|
||||
}
|
||||
|
||||
|
||||
#[test]
|
||||
fn test_fibo() {
|
||||
assert_eq!("jal zero,10504", print_instruction_debug(&Instruction::new(0x0500006f), 0x104b4));
|
||||
assert_eq!("blt a4,a5,104b8", print_instruction_debug(&Instruction::new(0xfaf740e3), 0x10518));
|
||||
assert_eq!("jal zero,10504", instruction_debug(&Instruction::new(0x0500006f), 0x104b4));
|
||||
assert_eq!("blt a4,a5,104b8", instruction_debug(&Instruction::new(0xfaf740e3), 0x10518));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mul_prog() {
|
||||
assert_eq!("addi sp,sp,-32", print_instruction_debug(&Instruction::new(0xfe010113), 0));
|
||||
assert_eq!("sd s0,24(sp)", print_instruction_debug(&Instruction::new(0x00813c23), 0));
|
||||
assert_eq!("addi s0,sp,32", print_instruction_debug(&Instruction::new(0x02010413), 0));
|
||||
assert_eq!("addi a5,zero,5", print_instruction_debug(&Instruction::new(0x00500793), 0));
|
||||
assert_eq!("sw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("lw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("addi a5,a4,0", print_instruction_debug(&Instruction::new(0x00070793), 0));
|
||||
assert_eq!("slliw a5,a5,0x2", print_instruction_debug(&Instruction::new(0x0027979b), 0));
|
||||
assert_eq!("addw a5,a5,a4", print_instruction_debug(&Instruction::new(0x00e787bb), 0));
|
||||
assert_eq!("sw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfef42423), 0));
|
||||
assert_eq!("lw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("mulw a5,a4,a5", print_instruction_debug(&Instruction::new(0x02f707bb), 0));
|
||||
assert_eq!("sw a5,-28(s0)", print_instruction_debug(&Instruction::new(0xfef42223), 0));
|
||||
assert_eq!("lw a5,-28(s0)", print_instruction_debug(&Instruction::new(0xfe442783), 0));
|
||||
assert_eq!("addi a4,a5,0", print_instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", print_instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("divw a5,a4,a5", print_instruction_debug(&Instruction::new(0x02f747bb), 0));
|
||||
assert_eq!("sw a5,-20(s0)", print_instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("addi a5,zero,0", print_instruction_debug(&Instruction::new(0x00000793), 0));
|
||||
assert_eq!("addi a0,a5,0", print_instruction_debug(&Instruction::new(0x00078513), 0));
|
||||
assert_eq!("ld s0,24(sp)", print_instruction_debug(&Instruction::new(0x01813403), 0));
|
||||
assert_eq!("addi sp,sp,32", print_instruction_debug(&Instruction::new(0x02010113), 0));
|
||||
assert_eq!("jalr zero,0(ra)", print_instruction_debug(&Instruction::new(0x00008067), 0));
|
||||
assert_eq!("addi sp,sp,-32", instruction_debug(&Instruction::new(0xfe010113), 0));
|
||||
assert_eq!("sd s0,24(sp)", instruction_debug(&Instruction::new(0x00813c23), 0));
|
||||
assert_eq!("addi s0,sp,32", instruction_debug(&Instruction::new(0x02010413), 0));
|
||||
assert_eq!("addi a5,zero,5", instruction_debug(&Instruction::new(0x00500793), 0));
|
||||
assert_eq!("sw a5,-20(s0)", instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("lw a5,-20(s0)", instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("addi a5,a4,0", instruction_debug(&Instruction::new(0x00070793), 0));
|
||||
assert_eq!("slliw a5,a5,0x2", instruction_debug(&Instruction::new(0x0027979b), 0));
|
||||
assert_eq!("addw a5,a5,a4", instruction_debug(&Instruction::new(0x00e787bb), 0));
|
||||
assert_eq!("sw a5,-24(s0)", instruction_debug(&Instruction::new(0xfef42423), 0));
|
||||
assert_eq!("lw a5,-20(s0)", instruction_debug(&Instruction::new(0xfec42783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("mulw a5,a4,a5", instruction_debug(&Instruction::new(0x02f707bb), 0));
|
||||
assert_eq!("sw a5,-28(s0)", instruction_debug(&Instruction::new(0xfef42223), 0));
|
||||
assert_eq!("lw a5,-28(s0)", instruction_debug(&Instruction::new(0xfe442783), 0));
|
||||
assert_eq!("addi a4,a5,0", instruction_debug(&Instruction::new(0x00078713), 0));
|
||||
assert_eq!("lw a5,-24(s0)", instruction_debug(&Instruction::new(0xfe842783), 0));
|
||||
assert_eq!("divw a5,a4,a5", instruction_debug(&Instruction::new(0x02f747bb), 0));
|
||||
assert_eq!("sw a5,-20(s0)", instruction_debug(&Instruction::new(0xfef42623), 0));
|
||||
assert_eq!("addi a5,zero,0", instruction_debug(&Instruction::new(0x00000793), 0));
|
||||
assert_eq!("addi a0,a5,0", instruction_debug(&Instruction::new(0x00078513), 0));
|
||||
assert_eq!("ld s0,24(sp)", instruction_debug(&Instruction::new(0x01813403), 0));
|
||||
assert_eq!("addi sp,sp,32", instruction_debug(&Instruction::new(0x02010113), 0));
|
||||
assert_eq!("jalr zero,0(ra)", instruction_debug(&Instruction::new(0x00008067), 0));
|
||||
}
|
||||
|
||||
}
|
||||
@ -266,7 +266,7 @@ impl Machine {
|
||||
let inst : Instruction = Instruction::new(val);
|
||||
self.print_status();
|
||||
println!("executing instruction : {:016x} at pc {:x}", val, self.pc);
|
||||
println!("{}", instruction::print_instruction_debug(&inst, self.pc as i32));
|
||||
println!("{}", instruction::instruction_debug(&inst, self.pc as i32));
|
||||
let trace = Self::string_registers(self);
|
||||
self.registers_trace.push_str(format!("{}\n", trace).as_str());
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user