Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Align with tabulations

Browse Source
This commit is contained in:
Samy Solhi 2022-11-16 17:37:04 +01:00
parent dcd2012c64
commit 802f80e96a
1 changed files with 59 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

118
src/print.rs
View File

@ -181,33 +181,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
name = names_op[ins.funct3 as usize]; name = names_op[ins.funct3 as usize];
} }
} }
format!("{} {}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
}, },
RISCV_OPI => { RISCV_OPI => {
// SHAMT OR IMM // SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI { if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI { if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("slrii {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} else { } else {
format!("srai {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} }
} else if ins.funct3 == RISCV_OPI_SLLI { } else if ins.funct3 == RISCV_OPI_SLLI {
format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} else { } else {
format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
} }
}, },
RISCV_LUI => { RISCV_LUI => {
format!("lui {}, 0x{:X}", reg_x[rd], ins.imm31_12) format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12)
}, },
RISCV_AUIPC => { RISCV_AUIPC => {
format!("auipc {}, {:X}", reg_x[rd], ins.imm31_12) format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12)
}, },
RISCV_JAL => { RISCV_JAL => {
if ins.rd == 0 { if ins.rd == 0 {
format!("j {}", ins.imm31_12.to_string()) format!("j\t{}", ins.imm31_12.to_string())
} else { } else {
format!("jal {}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
} }
}, },
RISCV_JALR => { RISCV_JALR => {
@ -215,52 +215,52 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
if ins.rs1 == 1 { if ins.rs1 == 1 {
"ret".to_string() "ret".to_string()
} else { } else {
format!("jr {:X}", ins.imm31_12) format!("jr\t{:X}", ins.imm31_12)
} }
} else { } else {
format!("jalr {}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
} }
}, },
RISCV_BR => { RISCV_BR => {
format!("{} {}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
}, },
RISCV_LD => { RISCV_LD => {
format!("{} {}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
}, },
RISCV_ST => { RISCV_ST => {
format!("{} {}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
}, },
RISCV_OPIW => { RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW { if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srlwi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("srawi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else if ins.funct3 == RISCV_OPIW_SLLIW { } else if ins.funct3 == RISCV_OPIW_SLLIW {
format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("{} {}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
} }
}, },
RISCV_OPW => { RISCV_OPW => {
if ins.funct7 == 1 { if ins.funct7 == 1 {
format!("{}w {}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
if ins.funct3 == RISCV_OP_ADD { if ins.funct3 == RISCV_OP_ADD {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
format!("addw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("subw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else if ins.funct3 == RISCV_OPW_SRW { } else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW { if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("sraw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else { } else {
format!("{} {}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} }
}, },
@ -286,11 +286,11 @@ mod test {
let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
assert_eq!("sub t3, a7, a6", print::print(sub, 0)); assert_eq!("sub\tt3, a7, a6", print::print(sub, 0));
assert_eq!("xor t3, a7, a6", print::print(xor, 0)); assert_eq!("xor\tt3, a7, a6", print::print(xor, 0));
assert_eq!("srl t3, a7, a6", print::print(slr, 0)); assert_eq!("srl\tt3, a7, a6", print::print(slr, 0));
assert_eq!("sra t3, a7, a6", print::print(sra, 0)); assert_eq!("sra\tt3, a7, a6", print::print(sra, 0));
assert_eq!("add t3, a7, a6", print::print(add, 0)); assert_eq!("add\tt3, a7, a6", print::print(add, 0));
} }
@ -303,21 +303,21 @@ mod test {
let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
let ori = decode::decode(0b00000000000_10001_110_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
let andi = decode::decode(0b000000000000_10001_111_11100_0010011); let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
assert_eq!("andi t3, a7, 0", print::print(andi, 0)); assert_eq!("andi\tt3, a7, 0", print::print(andi, 0));
assert_eq!("addi t3, a7, 0", print::print(addi, 0)); assert_eq!("addi\tt3, a7, 0", print::print(addi, 0));
assert_eq!("slli t3, a7, 0", print::print(slli, 0)); assert_eq!("slli\tt3, a7, 0", print::print(slli, 0));
assert_eq!("slti t3, a7, 0", print::print(slti, 0)); assert_eq!("slti\tt3, a7, 0", print::print(slti, 0));
assert_eq!("sltiu t3, a7, 0", print::print(sltiu, 0)); assert_eq!("sltiu\tt3, a7, 0", print::print(sltiu, 0));
assert_eq!("xori t3, a7, 0", print::print(xori, 0)); assert_eq!("xori\tt3, a7, 0", print::print(xori, 0));
assert_eq!("ori t3, a7, 0", print::print(ori, 0)); assert_eq!("ori\tt3, a7, 0", print::print(ori, 0));
} }
#[test] #[test]
fn test_lui() { fn test_lui() {
let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui = decode::decode(0b01110001000011111000_11100_0110111);
let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
assert_eq!("lui t3, 0x710F8000", print::print(lui, 0)); assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0));
assert_eq!("lui t3, 0xF10F8000", print::print(lui_negatif, 0)); assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0));
} }
#[test] #[test]
@ -330,14 +330,14 @@ mod test {
let lhu = decode::decode(0b010111110000_10001_101_11100_0000011); let lhu = decode::decode(0b010111110000_10001_101_11100_0000011);
let ld = decode::decode(0b010111110000_10001_011_11100_0000011); let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
// TODO: imm négatif produit une erreur
assert_eq!("lb t3, 1520(a7)", print::print(lb, 0)); assert_eq!("lb\tt3, 1520(a7)", print::print(lb, 0));
assert_eq!("lh t3, 1520(a7)", print::print(lh, 0)); assert_eq!("lh\tt3, 1520(a7)", print::print(lh, 0));
assert_eq!("lw t3, 1520(a7)", print::print(lw, 0)); assert_eq!("lw\tt3, 1520(a7)", print::print(lw, 0));
assert_eq!("lbu t3, 1520(a7)", print::print(lbu, 0)); assert_eq!("lbu\tt3, 1520(a7)", print::print(lbu, 0));
assert_eq!("lhu t3, 1520(a7)", print::print(lhu, 0)); assert_eq!("lhu\tt3, 1520(a7)", print::print(lhu, 0));
assert_eq!("ld t3, 1520(a7)", print::print(ld, 0)); assert_eq!("ld\tt3, 1520(a7)", print::print(ld, 0));
assert_eq!("lwu t3, 1520(a7)", print::print(lwu, 0)); assert_eq!("lwu\tt3, 1520(a7)", print::print(lwu, 0));
} }
#[test] #[test]
@ -347,10 +347,10 @@ mod test {
let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
assert_eq!("addw t3, a7, a6", print::print(addw, 0)); assert_eq!("addw\tt3, a7, a6", print::print(addw, 0));
assert_eq!("sllw t3, a7, a6", print::print(sllw, 0)); assert_eq!("sllw\tt3, a7, a6", print::print(sllw, 0));
assert_eq!("srlw t3, a7, a6", print::print(srlw, 0)); assert_eq!("srlw\tt3, a7, a6", print::print(srlw, 0));
assert_eq!("sraw t3, a7, a6", print::print(sraw, 0)); assert_eq!("sraw\tt3, a7, a6", print::print(sraw, 0));
} }
#[test] #[test]
@ -358,9 +358,9 @@ mod test {
let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
assert_eq!("addiw t3, a7, 0", print::print(addiw, 0)); assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0));
assert_eq!("slli t3, a7, a6", print::print(slliw, 0)); assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0));
assert_eq!("srai t3, a7, 17", print::print(srai, 0)); assert_eq!("srai\tt3, a7, 17", print::print(srai, 0));
} }
@ -372,12 +372,12 @@ mod test {
let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
assert_eq!("blt a7, a6, 0", print::print(blt, 0)); assert_eq!("blt\ta7, a6, 0", print::print(blt, 0));
assert_eq!("bge a7, a6, 0", print::print(bge, 0)); assert_eq!("bge\ta7, a6, 0", print::print(bge, 0));
assert_eq!("bltu a7, a6, 0", print::print(bltu, 0)); assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0));
assert_eq!("bgeu a7, a6, 0", print::print(bgeu, 0)); assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0));
assert_eq!("bne a7, a6, 0", print::print(bne, 0)); assert_eq!("bne\ta7, a6, 0", print::print(bne, 0));
assert_eq!("beq a7, a6, 0", print::print(beq, 0)); assert_eq!("beq\ta7, a6, 0", print::print(beq, 0));
} }
} }