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Add user_stack_size to Machine and use it for threads sp

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This commit is contained in:
Quentin Legot
2023-05-09 17:01:52 +02:00
parent 7d29b92eba
commit 7be0c0accc
6 changed files with 34 additions and 16 deletions
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21
src/simulator/machine.rs
View File

@ -96,6 +96,7 @@ pub struct Machine {
//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
num_phy_page: u64,
pub page_size: u64,
pub user_stack_size: u64,
/// Current machine status
pub status: MachineStatus
}
@ -115,7 +116,8 @@ impl Machine {
let num_phy_page = *settings.get(&MachineSettingKey::NumPhysPages).unwrap();
let page_size = *settings.get(&MachineSettingKey::PageSize).unwrap();
let mem_size = (page_size*num_phy_page*100_000) as usize;
let user_stack_size = *settings.get(&MachineSettingKey::UserStackSize).unwrap();
let mem_size = (page_size*num_phy_page) as usize;
Machine {
debug,
@ -129,7 +131,8 @@ impl Machine {
registers_trace : String::from(""),
status: MachineStatus::SystemMode,
num_phy_page,
page_size
page_size,
user_stack_size
}
}
@ -425,10 +428,10 @@ impl Machine {
RISCV_OPI_XORI => compute(&core::ops::BitXor::bitxor, rs1, imm12),
RISCV_OPI_ORI => compute(&core::ops::BitOr::bitor, rs1, imm12),
RISCV_OPI_ANDI => compute(&core::ops::BitAnd::bitand, rs1, imm12),
RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, imm12),
RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, shamt),
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
} else {
} else { // SRAI
compute(&core::ops::Shr::shr, rs1, shamt)
}
_ => Err(format!("Unreachable in opi_instruction match! Instruction was {:?}", inst))?
@ -501,8 +504,8 @@ impl Machine {
let local_data = self.int_reg.get_reg(inst.rs1);
let result = match inst.funct3 {
RISCV_OPIW_ADDIW => local_data + inst.imm12_I_signed as i64,
RISCV_OPIW_SLLIW => local_data << inst.shamt,
RISCV_OPIW_SRW => (local_data >> inst.shamt) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.shamt as usize] as i64 } else { 1 },
RISCV_OPIW_SLLIW => local_data << inst.rs2,
RISCV_OPIW_SRW => (local_data >> inst.rs2) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.rs2 as usize] as i64 } else { 1 },
_ => Err(format!("Unreachable in op_instruction match! Instruction was {:?}", inst))?
};
self.int_reg.set_reg(inst.rd, result);
@ -519,7 +522,7 @@ impl Machine {
// Match case for multiplication operations (in standard extension RV32M)
match inst.funct3 {
RISCV_OPW_M_MULW => self.int_reg.set_reg(inst.rd, local_data_a * local_data_b),
RISCV_OPW_M_MULW => self.int_reg.set_reg(inst.rd, (local_data_a * local_data_b) & 0xffffffff),
RISCV_OPW_M_DIVW => self.int_reg.set_reg(inst.rd, local_data_a / local_data_b),
RISCV_OPW_M_DIVUW => self.int_reg.set_reg(inst.rd, local_data_a_unsigned / local_data_b_unsigned),
RISCV_OPW_M_REMW => self.int_reg.set_reg(inst.rd, local_data_a % local_data_b),
@ -538,9 +541,9 @@ impl Machine {
},
RISCV_OPW_SLLW => self.int_reg.set_reg(inst.rd, local_dataa << (local_datab & 0x1f)),
RISCV_OPW_SRW => if inst.funct7 == RISCV_OPW_SRW_SRLW {
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f) & self.shiftmask[32 + local_datab as usize] as i64)
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab /* & 0x1f */) & self.shiftmask[32 + local_datab as usize] as i64)
} else { // SRAW
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f))
self.int_reg.set_reg(inst.rd, local_dataa >> (local_datab /* & 0x1f */))
},
_ => Err(format!("Unreachable in opw_instruction match! Instruction was {:?}", inst))?
}

2
src/simulator/mod.rs
View File

@ -214,7 +214,7 @@ pub mod global {
///
/// Shift left logical immediate
///
/// `SLLI rd, rs1, shamt` => `rd <- rs1 >> shamt`
/// `SLLI rd, rs1, shamt` => `rd <- rs1 << shamt`
pub const RISCV_OPI_SLLI: u8 = 0x1;
/// Shift right immediate, may be SRAI or SRLI
pub const RISCV_OPI_SRI: u8 = 0x5;