Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

RISCV_OP fixed

Browse Source
This commit is contained in:
Samy Solhi 2022-11-09 14:37:19 +01:00
parent 673c2c8d20
commit 7a89d06f36
1 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/print.rs
View File

@ -146,9 +146,25 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let name: &str; let name: &str;
if ins.funct7 == 1 { // Use mul array if ins.funct7 == 1 { // Use mul array
name = names_mul[ins.funct3 as usize] name = names_mul[ins.funct3 as usize]
} else {
if ins.funct3 == RISCV_OP_ADD {
// Add or Sub
if ins.funct7 == RISCV_OP_ADD_ADD {
name = "add";
} else {
name = "sub";
}
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else { } else {
name = names_op[ins.funct3 as usize]; name = names_op[ins.funct3 as usize];
} }
}
format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string()) format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string())
}, },
RISCV_OPI => { RISCV_OPI => {