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Update registers access on RISCV_OP

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This commit is contained in:
Quentin Legot 2023-02-01 17:04:10 +01:00
parent 069a8e5741
commit 67ebff7ad0
1 changed files with 13 additions and 13 deletions
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26
src/simulator/machine.rs
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@ -295,9 +295,9 @@ impl Machine {
}, },
RISCV_OPI_SRI => { RISCV_OPI_SRI => {
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64);
} else { // SRAI } else { // SRAI
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt);
} }
} }
_ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); }
@ -308,17 +308,17 @@ impl Machine {
if inst.funct7 == 1 { if inst.funct7 == 1 {
match inst.funct3 { match inst.funct3 {
RISCV_OP_M_MUL => { RISCV_OP_M_MUL => {
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_MULH => { RISCV_OP_M_MULH => {
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_MULHSU => { RISCV_OP_M_MULHSU => {
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
/* /*
@ -326,13 +326,13 @@ impl Machine {
* WHAT DA HECK * WHAT DA HECK
*/ */
RISCV_OP_M_MULHU => { RISCV_OP_M_MULHU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128; long_result = (unsigned_reg1 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_DIV => { RISCV_OP_M_DIV => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize));
} }
_ => { _ => {
panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");