From 651e03a446cabefcdd6b366de3a0560a613748bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Fran=C3=A7ois=20Autin?=
 <francois.autin@etudiant.univ-rennes1.fr>
Date: Sat, 25 Mar 2023 15:37:14 +0100
Subject: [PATCH] :memo: :refactor: Form and documentation updates

---
 src/simulator/machine.rs | 68 ++++++++++++++++++++--------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index 8cb3b8c..c721876 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -94,19 +94,16 @@ impl Machine {
 			value >>= 1;
 		}
 
-		let mut ret = Machine {
+		Machine {
 			pc : 0,
 			sp: 0,
-			int_reg : Register::<i64>::init(),
+			int_reg : { let mut r = Register::<i64>::init(); r.set_reg(10, -1); r },
 			fp_reg : Register::<f32>::init(),
 			main_memory : vec![0_u8; MEM_SIZE],
 			shiftmask,
 			interrupt: Interrupt::new(),
 			registers_trace : String::from("")
-		};
-
-		ret.int_reg.set_reg(10, -1);
-		ret
+		}
 	}
 
 	/// Read from main memory of the machine
@@ -242,58 +239,61 @@ impl Machine {
 		self.pc += 4;
 		
 		match inst.opcode {
+			// Treatment for: LOAD UPPER IMMEDIATE INSTRUCTION
 			RISCV_LUI => {
 				self.int_reg.set_reg(inst.rd, inst.imm31_12 as i64);
 				Ok(())
 			},
+
+			// Treatment for: ADD UPPER IMMEDIATE TO PC INSTRUCTION
 			RISCV_AUIPC => {
 				self.int_reg.set_reg(inst.rd, self.pc as i64 - 4 + inst.imm31_12 as i64);
 				Ok(())
 			},
+
+			// Treatement for: JUMP AND LINK INSTRUCTIONS (direct jump)
 			RISCV_JAL => {
 				self.int_reg.set_reg(inst.rd, self.pc as i64);
 				self.pc = (self.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64;
 				Ok(())
 			},
+
+			// Treatment for: JUMP AND LINK REGISTER INSTRUCTIONS (indirect jump)
 			RISCV_JALR => {
 				let tmp = self.pc;
 				self.pc = (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe;
 				self.int_reg.set_reg(inst.rd, tmp as i64);
 				Ok(())
 			},
+
   			// Treatment for: BRANCH INSTRUCTIONS
-			RISCV_BR => {
-				self.branch_instruction(inst)
-			},
+			RISCV_BR => 	self.branch_instruction(inst),
+
     		// Treatment for: LOAD INSTRUCTIONS
-			RISCV_LD => {
-				self.load_instruction(inst)
-			},
-			// store instructions
-			RISCV_ST => {
-				self.store_instruction(inst)
-			},
+			RISCV_LD => 	self.load_instruction(inst),
+
+			// Treatment for: STORE INSTRUCTIONS
+			RISCV_ST => 	self.store_instruction(inst),
+
     		// Treatment for: OPI INSTRUCTIONS
-			RISCV_OPI => {
-				self.opi_instruction(inst)
-			},
-			RISCV_OP => {
-				self.op_instruction(inst)
-			},
+			RISCV_OPI =>	self.opi_instruction(inst),
+
+			// Treatment for: OP INSTRUCTIONS
+			RISCV_OP => 	self.op_instruction(inst),
+
 			// Treatment for OPIW INSTRUCTIONS
-			RISCV_OPIW => {
-				self.opiw_instruction(inst)
-			},
+			RISCV_OPIW =>	self.opiw_instruction(inst),
+
     		// Treatment for: OPW INSTRUCTIONS
-			RISCV_OPW => self.opw_instruction(inst),
-    		// Treatment for: Simple floating point extension
-			RISCV_FP => self.fp_instruction(inst),
-			// Treatment for: System instructions
-			RISCV_SYSTEM => {
-				// temporary return value to stop the loop of run 
-				// before we can use system call
-				Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str()))
-			},
+			RISCV_OPW =>	self.opw_instruction(inst),
+
+    		// Treatment for: FLOATING POINT INSTRUCTIONS
+			RISCV_FP =>		self.fp_instruction(inst),
+
+			// Treatment for: SYSTEM CALLS
+			RISCV_SYSTEM => Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str())),
+
+			// Default case
 			_ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc).as_str()))
 		}
 	}