From 40374bf26f5a9fc403fc57c47356e69980e6047b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Mon, 23 Jan 2023 14:29:37 +0100 Subject: [PATCH] F extension documentation done --- src/simulator/mod.rs | 91 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 9f3f208..6aef6be 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -418,10 +418,18 @@ pub mod global { pub const RISCV_FP_FSGN: u8 = 0x10; // fmin or fmax instructions pub const RISCV_FP_MINMAX: u8 = 0x14; + /// fcvt.w instructions + /// + /// convert fp to integer pub const RISCV_FP_FCVTW: u8 = 0x60; + /// fmv.x.w or fclass.s instruction pub const RISCV_FP_FMVXFCLASS: u8 = 0x70; + /// floating points comparaison instructions pub const RISCV_FP_FCMP: u8 = 0x50; pub const RISCV_FP_FEQS: u8 = 0x53; + /// fcvt.s instructions + /// + /// Convert integer to fp pub const RISCV_FP_FCVTS: u8 = 0x68; pub const RISCV_FP_FCVTDS: u8 = 0x21; @@ -444,22 +452,101 @@ pub mod global { /// `fsgnjx.s rd, rs1, rs2` => `rd <- {rs1[31] ^ rs2[31], rs1[30:0]}` pub const RISCV_FP_FSGN_JX: u8 = 0x2; + /// Type: R + /// + /// write the smaller number between rs1 and rs2 to rd + /// + /// `fmin.s rd, rs1, rs2` => `rd <- min(rs1, rs2)` pub const RISCV_FP_MINMAX_MIN: u8 = 0x0; + /// type: R + /// + /// Write the larger number between rs1 and rs2 to rd + /// + /// `fmax.s rd, rs1, rs2` => `rd <- max(rs1, rs2)` pub const RISCV_FP_MINMAX_MAX: u8 = 0x1; - + + /// Type: R + /// + /// Convert a floating point number in register to a signed 32-bit integer and write it in integer register + /// + /// `fcvt.w.s rd, rs1` => `rd <- rs1_f32 as i32` + /// + /// rd is integer register and rs1 is floating point register pub const RISCV_FP_FCVTW_W: u8 = 0x0; + /// Type: R + /// + /// Convert a floating point number in register to a unsigned 32 bit integer and write it in integer register + /// + /// `fcvt.wu.s rd, rs1` => `rd <- rs1_f32 as u32` pub const RISCV_FP_FCVTW_WU: u8 = 0x1; + /// Type : R + /// + /// Convert signed 32 bit integer in register to a floating point number and write it in fp register + /// + /// `fcvt.s.w rd, rs1` => `rd <- rs1_s32 as f32` pub const RISCV_FP_FCVTS_W: u8 = 0x0; + /// Type: R + /// + /// Convert unsigned 32 bit integer in register to a floating point number and write it in fp register + /// + /// `fcvt.s.wu rd, rs1` => `rd <- rs1_u32 as f32` pub const RISCV_FP_FCVTS_WU: u8 = 0x1; - + /// Type: R + /// + /// Move floating point value in register to integer register, bits value aren't modified during the process + /// + /// On rv64, the lower 32 bits of the integer register are transfered, for the upper 32 bits, values are filles with copies of the floating point number's sign bit + /// + /// `fmv.x.w rd ,rs1` => `rd[31,0] <- rs1; rd[63:32] <- rs[31]` pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; + /// Type: R + /// + /// examine the value given in fp register rs1 and writes to integer register rd a 10 bit mask that indicates the class of the fp number. + /// Format is described here: + /// + /// | rd bit | meaning | + /// |--------|------------------------------------| + /// | 0 | rs1 is -infinite | + /// | 1 | rs1 is a negative normal number | + /// | 2 | rs1 is a negative subnormal number | + /// | 3 | rs1 is -0 | + /// | 4 | rs1 is +0 | + /// | 5 | rs1 is a positive subnormal number | + /// | 6 | rs1 is a positive normal number | + /// | 7 | rs1 is +infinite | + /// | 8 | rs1 is a signaling NaN | + /// | 9 | rs1 is a quiet NaN | + /// + /// All others bit in rd are cleared pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; + /// Type: R + /// + /// Quiet equal comparaison, NaN cause an invalid operation exception + /// + /// `feq.s rd, rs1, rs2` => `rd <- rs1 == rs2` pub const RISCV_FP_FCMP_FEQ: u8 = 2; + /// Type: R + /// + /// Quiet less comparaison, NaN cause an invalid operation exception + /// + /// `flt.s rd, rs1, rs2` => `rdf <- rs1 < rs2` pub const RISCV_FP_FCMP_FLT: u8 = 1; + /// Type: R + /// + /// Quiet less or equal comparaison, NaN cause an invalid operation exception + /// + /// `fle.s rd, rs1, rs2` => `rd <- rs1 <= rs2` pub const RISCV_FP_FCMP_FLE: u8 = 0; + /// Type : R + /// + /// Move floating point value in integer register to the fp register. Bits aren't modified in the transfer + /// + /// On rv64, only the lower 32 bits in the integer register are transfered. + /// + /// `fmv.w.x rd, rs1` => `rd <- rs1[31:0]` pub const RISCV_FP_FMVW: u8 = 0x78; /// Integer, multiplication and division extension