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Added OPIW OPs and made some fix (see description)

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Fix some warning which appear on clippy
Fix print with 2 OPIW operations
Fix doc in mod.rs
This commit is contained in:
Quentin Legot
2023-02-04 18:16:52 +01:00
parent 83c212199e
commit 3762547402
4 changed files with 38 additions and 11 deletions
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6
src/simulator/mod.rs
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@ -303,7 +303,7 @@ pub mod global {
///
/// Shift right logical immediate word (RV64I only)
///
/// `SLLIW rd, rs1, imm12` => `rd <- rs1 >> imm12`
/// `SLLIW rd, rs1, imm12` => `rd <- rs1 >> shamt`
pub const RISCV_OPIW_SLLIW: u8 = 0x1;
/// Shift right immediate instructions (logical or arithmetic depend of func7)
@ -312,7 +312,7 @@ pub mod global {
///
/// Shift right logical immediate word (RV64I only)
///
/// `SRLIW rd, rs1, imm12` => `rd <- rs1 >> imm12`
/// `SRLIW rd, rs1, imm12` => `rd <- rs1 >> shamt`
///
/// Complete left bits by a zero, should be used with an unsigned value in most case
pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0;
@ -320,7 +320,7 @@ pub mod global {
///
/// Shift right arithmetic immediate word (RV64I only)
///
/// `SRAIW rd, rs1, imm12` => `rd <- rs1 >> imm12`
/// `SRAIW rd, rs1, imm12` => `rd <- rs1 >> shamt`
///
/// Keep sign bit
pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20;