Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

♻️ OPI instruction done

Browse Source
This commit is contained in:
François Autin 2023-03-27 14:59:22 +02:00
parent ba8e36ea90
commit 288703321e
No known key found for this signature in database
GPG Key ID: 343F5D382E1DD77C
1 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/simulator/machine.rs
View File

@ -385,24 +385,24 @@ impl Machine {
/// Executes RISC-V Integer Register-Immediate Instructions on the machine
fn opi_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut compute = |operation: &dyn Fn (i64, i64) -> i64| {
self.int_reg.set_reg(inst.rd, operation(self.int_reg.get_reg(inst.rs1), inst.imm12_I_signed as i64));
let rs1 = self.int_reg.get_reg(inst.rs1);
let imm12 = inst.imm12_I_signed as i64;
let shamt = inst.shamt as i64;
let mut compute = |operation: &dyn Fn (i64, i64) -> i64, a, b| {
self.int_reg.set_reg(inst.rd, operation(a, b));
Ok(())
};
match inst.funct3 {
RISCV_OPI_ADDI => compute(&std::ops::Add::add),
RISCV_OPI_SLTI => compute(&|a, b| { (a < b) as i64 }),
RISCV_OPI_XORI => compute(&|a, b| { a ^ b }),
RISCV_OPI_ORI => compute(&|a, b| { a | b }),
RISCV_OPI_ANDI => compute(&|a, b| { a & b }),
RISCV_OPI_SLLI => compute(&|a, b| { a << b }),
RISCV_OPI_SRI => {
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
self.int_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) >> inst.shamt) & self.shiftmask[inst.shamt as usize] as i64)
} else { // SRAI
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> inst.shamt)
}
Ok(())
RISCV_OPI_ADDI => compute(&std::ops::Add::add, rs1, imm12),
RISCV_OPI_SLTI => compute(&|a, b| (a < b) as i64, rs1, imm12),
RISCV_OPI_XORI => compute(&core::ops::BitXor::bitxor, rs1, imm12),
RISCV_OPI_ORI => compute(&core::ops::BitOr::bitor, rs1, imm12),
RISCV_OPI_ANDI => compute(&core::ops::BitAnd::bitand, rs1, imm12),
RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, imm12),
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
} else {
compute(&|a, b| { a >> b }, rs1, shamt)
}
_ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str()))
}