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♻️ OPI instruction done

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François Autin 2023-03-27 14:59:22 +02:00
parent ba8e36ea90
commit 288703321e
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1 changed files with 15 additions and 15 deletions
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src/simulator/machine.rs
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@ -385,24 +385,24 @@ impl Machine {
/// Executes RISC-V Integer Register-Immediate Instructions on the machine /// Executes RISC-V Integer Register-Immediate Instructions on the machine
fn opi_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> { fn opi_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut compute = |operation: &dyn Fn (i64, i64) -> i64| { let rs1 = self.int_reg.get_reg(inst.rs1);
self.int_reg.set_reg(inst.rd, operation(self.int_reg.get_reg(inst.rs1), inst.imm12_I_signed as i64)); let imm12 = inst.imm12_I_signed as i64;
let shamt = inst.shamt as i64;
let mut compute = |operation: &dyn Fn (i64, i64) -> i64, a, b| {
self.int_reg.set_reg(inst.rd, operation(a, b));
Ok(()) Ok(())
}; };
match inst.funct3 { match inst.funct3 {
RISCV_OPI_ADDI => compute(&std::ops::Add::add), RISCV_OPI_ADDI => compute(&std::ops::Add::add, rs1, imm12),
RISCV_OPI_SLTI => compute(&|a, b| { (a < b) as i64 }), RISCV_OPI_SLTI => compute(&|a, b| (a < b) as i64, rs1, imm12),
RISCV_OPI_XORI => compute(&|a, b| { a ^ b }), RISCV_OPI_XORI => compute(&core::ops::BitXor::bitxor, rs1, imm12),
RISCV_OPI_ORI => compute(&|a, b| { a | b }), RISCV_OPI_ORI => compute(&core::ops::BitOr::bitor, rs1, imm12),
RISCV_OPI_ANDI => compute(&|a, b| { a & b }), RISCV_OPI_ANDI => compute(&core::ops::BitAnd::bitand, rs1, imm12),
RISCV_OPI_SLLI => compute(&|a, b| { a << b }), RISCV_OPI_SLLI => compute(&core::ops::Shl::shl, rs1, imm12),
RISCV_OPI_SRI => { RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
self.int_reg.set_reg(inst.rd, (self.int_reg.get_reg(inst.rs1) >> inst.shamt) & self.shiftmask[inst.shamt as usize] as i64) } else {
} else { // SRAI compute(&|a, b| { a >> b }, rs1, shamt)
self.int_reg.set_reg(inst.rd, self.int_reg.get_reg(inst.rs1) >> inst.shamt)
}
Ok(())
} }
_ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str())) _ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str()))
} }