diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index d27dc60..2c6f035 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -342,42 +342,42 @@ impl Machine {
 					match inst.funct3 {
 						RISCV_OP_ADD => {
 							if inst.funct7 == RISCV_OP_ADD_ADD {
-								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
+								machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize));
 							} else {
-								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
+								machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize));
 							}
 						},
 						RISCV_OP_SLL => {
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
+							machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f));
 						},
 						RISCV_OP_SLT => {
-							if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
-								machine.int_reg[inst.rd as usize] = 1;
+							if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
+								machine.int_reg.set_reg(inst.rd as usize, 1);
 							} else {
-								machine.int_reg[inst.rd as usize] = 0;
+								machine.int_reg.set_reg(inst.rd as usize, 0);
 							}
 						},
 						RISCV_OP_SLTU => {
-							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
-							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
+							unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
+							unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
 							if unsigned_reg1 < unsigned_reg2 {
-								machine.int_reg[inst.rd as usize] = 1;
+								machine.int_reg.set_reg(inst.rd as usize, 1);
 							} else {
-								machine.int_reg[inst.rd as usize] = 0;
+								machine.int_reg.set_reg(inst.rd as usize, 0);
 							}
 						},
 						RISCV_OP_XOR => {
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
+							machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize));
 						},
 						RISCV_OP_SR => {
 						// RISCV_OP_SR_SRL inaccessible
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
+							machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize));
 						},
 						RISCV_OP_OR => {
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
+							machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize));
 						},
 						RISCV_OP_AND => {
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
+							machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize));
 						},
 						_ => {
 							panic!("RISCV_OP undefined case\n");
@@ -389,53 +389,53 @@ impl Machine {
     		// Treatment for: OPW INSTRUCTIONS
 			RISCV_OPW => {
 				if inst.funct7 == 1 {
-					let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
-					let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
-					let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
-					let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
+					let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
+					let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
+					let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
+					let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
 
 					// Match case for multiplication operations (in standard extension RV32M)
 					match inst.funct3 {
 						RISCV_OPW_M_MULW => {
-							machine.int_reg[inst.rd as usize] = local_data_a * local_data_b;
+							machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b);
 						},
 						RISCV_OPW_M_DIVW => {
-							machine.int_reg[inst.rd as usize] = local_data_a / local_data_b;
+							machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b);
 						},
 						RISCV_OPW_M_DIVUW => {
-							machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned;
+							machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned);
 						},
 						RISCV_OPW_M_REMW => {
-							machine.int_reg[inst.rd as usize] = local_data_a % local_data_b;
+							machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b);
 						},
 						RISCV_OPW_M_REMUW => {
-							machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned;
+							machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned);
 						},
 						_ => {
 							panic!("this instruction ({}) doesn't exists", inst.value);
 						}
 					}
 				} else {
-					let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
-					let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
+					let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
+					let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
 
 					// Match case for base OP operation
 					match inst.funct3 {
 						RISCV_OPW_ADDSUBW => {
 							if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
-								machine.int_reg[inst.rd as usize] = local_dataa + local_datab;
+								machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab);
 							} else { // SUBW
-								machine.int_reg[inst.rd as usize] = local_dataa - local_datab;
+								machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab);
 							}
 						},
 						RISCV_OPW_SLLW => {
-							machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f);
+							machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f));
 						},
 						RISCV_OPW_SRW => {
 							if inst.funct7 == RISCV_OPW_SRW_SRLW {
-								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64;
+								machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64);
 							} else { // SRAW
-								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
+								machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f));
 							}
 						},
 						_ => {