From ad960a46e0e5b4297286efd0b44eba72b86880a7 Mon Sep 17 00:00:00 2001
From: Quentin Legot <legotquentin@gmail.com>
Date: Wed, 23 Nov 2022 16:04:21 +0100
Subject: [PATCH] Comments has been standardized, remove some warnings

---
 src/machine.rs | 40 +++++++++++++++++++++-------------------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/src/machine.rs b/src/machine.rs
index 1d6a0cb..c055377 100644
--- a/src/machine.rs
+++ b/src/machine.rs
@@ -1,7 +1,7 @@
 use crate::decode::*;
 use crate::print::*;
 
-// doit disparaitre
+/// doit disparaitre
 const MEM_SIZE : usize= 4096;
 
 
@@ -38,10 +38,11 @@ impl Machine {
 	}
 
 
-	/*
-	execute the instructions table of a machine putted in param
-	@param machine which contains a table of instructions
-	*/
+	/// Execute the instructions table of a machine putted in param
+	/// 
+	/// ### Parameters
+	/// 
+	/// - **machine** which contains a table of instructions
 	pub fn run(machine : Machine){
 		let mut m = machine;
 		loop{
@@ -49,10 +50,11 @@ impl Machine {
 		}
 	}
 
-	/*
-	execute the current instruction
-	@param machine which contains a table of instructions and a pc to the actual instruction
-	*/
+	/// execute the current instruction
+	/// 
+	/// ### Parameters
+	/// 
+	/// - **machine** which contains a table of instructions and a pc to the actual instruction
 	pub fn one_instruction(machine :&mut Machine) {
 	
 		let mut unsigned_reg1 : u64 = 0;
@@ -108,7 +110,7 @@ impl Machine {
 						if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
 							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize];
 						} else { // SRAI
-							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt);	
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;	
 						}
 					}
 					_ => { println!("{} inconnu", inst.funct3); }
@@ -121,7 +123,7 @@ impl Machine {
 			},
 			
 			RISCV_OP => {
-				if(inst.funct7 == 1){
+				if inst.funct7 == 1{
 					match inst.funct3 {
 						RISCV_OP_M_MUL => {
 							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
@@ -148,7 +150,7 @@ impl Machine {
 	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u32;
 						},
 						RISCV_OP_M_DIV => {
-							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
 						}
 						_ => {
 							println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
@@ -232,26 +234,26 @@ impl Machine {
 						}
 					}
 				} else {
-					let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
-					let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
+					let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
+					let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
 
 					// Match case for base OP operation
 					match inst.funct3 {
 						RISCV_OPW_ADDSUBW => {
 							if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
-								machine.int_reg[inst.rd as usize] = localDataa + localDatab;
+								machine.int_reg[inst.rd as usize] = local_dataa + local_datab;
 							} else { // SUBW
-								machine.int_reg[inst.rd as usize] = localDataa - localDatab;
+								machine.int_reg[inst.rd as usize] = local_dataa - local_datab;
 							}
 						},
 						RISCV_OPW_SLLW => {
-							machine.int_reg[inst.rd as usize] = localDataa << (localDatab & 0x1f);
+							machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f);
 						},
 						RISCV_OPW_SRW => {
 							if inst.funct7 == RISCV_OPW_SRW_SRLW {
-								machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f) & machine.shiftmask[32 + localDatab as usize];
+								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize];
 							} else { // SRAW
-								machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f);
+								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
 							}
 						},
 						_ => {