From 240f029881a1c975f3b88b864ea9c640a78044bf Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 9 Nov 2022 17:35:16 +0100 Subject: [PATCH] simulate some instructions --- src/machine.rs | 30 ++++++++++++++++++++++++++++-- src/main.rs | 8 +++----- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/machine.rs b/src/machine.rs index bc53171..71a2ed5 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -1,5 +1,3 @@ -#[warn(unused_parens)] - use crate::decode::*; use crate::print::*; @@ -26,12 +24,40 @@ impl Machine { println!("ERROR : number max of instructions rushed"); return machine; } + let inst : Instruction = decode(machine.instructions[machine.pc as usize]); machine.pc += 1; + match (inst.opcode) { RISCV_LUI => { machine.int_reg[inst.rd as usize] = inst.imm31_12; }, + + //****************************************************************************************** + // Treatment for: OPI INSTRUCTIONS + RISCV_OPI => { + match (inst.funct3) { + RISCV_OPI_ADDI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32; + }, + RISCV_OPI_SLTI => { + machine.int_reg[inst.rd as usize] = + if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 }; + }, + RISCV_OPI_XORI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32; + }, + RISCV_OPI_ORI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32; + }, + RISCV_OPI_ANDI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32; + }, + RISCV_OPI_SLLI => { + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + } + } + }, } diff --git a/src/main.rs b/src/main.rs index 9eb5d76..f21a6d7 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,12 +1,10 @@ mod decode; mod print; mod machine; +use machine::Machine; fn main() { - let instr = decode::decode(98); - println!("{}", print::print(instr, 0)); - - let mut m = machine::Machine::_init_machine(); + let mut m = Machine::_init_machine(); m.instructions[0] = 0x37; - machine::Machine::oneInstruction(m); + Machine::oneInstruction(m); }