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♻️ Simplified branch_instruction

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François Autin 2023-03-27 15:37:30 +02:00
parent ff93fab832
commit 2162232199
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 13 additions and 34 deletions
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47
src/simulator/machine.rs
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@ -308,40 +308,19 @@ impl Machine {
/// Treatement for Branch instructions /// Treatement for Branch instructions
fn branch_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> { fn branch_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
match inst.funct3 { let op = match inst.funct3 {
RISCV_BR_BEQ => { RISCV_BR_BEQ => |a, b| a == b,
if self.int_reg.get_reg(inst.rs1) == self.int_reg.get_reg(inst.rs2) { RISCV_BR_BNE => |a, b| a != b,
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64; RISCV_BR_BLT => |a, b| a < b,
} RISCV_BR_BGE => |a, b| a >= b,
}, RISCV_BR_BLTU => |a, b| a < b,
RISCV_BR_BNE => { RISCV_BR_BGEU => |a, b| a >= b,
if self.int_reg.get_reg(inst.rs1) != self.int_reg.get_reg(inst.rs2) { _ => unreachable!()
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64; };
} let rs1 = self.int_reg.get_reg(inst.rs1);
}, let rs2 = self.int_reg.get_reg(inst.rs2);
RISCV_BR_BLT => { if op(rs1, rs2) {
if self.int_reg.get_reg(inst.rs1) < self.int_reg.get_reg(inst.rs2) { self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
}
},
RISCV_BR_BGE => {
if self.int_reg.get_reg(inst.rs1) >= self.int_reg.get_reg(inst.rs2) {
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
}
},
RISCV_BR_BLTU => {
if self.int_reg.get_reg(inst.rs1) < self.int_reg.get_reg(inst.rs2) {
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
}
},
RISCV_BR_BGEU => {
if self.int_reg.get_reg(inst.rs1) >= self.int_reg.get_reg(inst.rs2) {
self.pc = (self.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
}
},
_ => {
panic!("In BR switch case, this should never happen... Instr was {}", inst.value);
}
} }
Ok(()) Ok(())
} }