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Fixed R32F

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This commit is contained in:
Samy Solhi 2023-02-15 14:33:40 +01:00
parent a9a86b674b
commit 06f0be9ece
1 changed files with 22 additions and 25 deletions
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47
src/simulator/print.rs
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@ -142,79 +142,76 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let name: &str; let name: &str;
match ins.funct7 { match ins.funct7 {
RISCV_FP_ADD => { RISCV_FP_ADD => {
name = "fadd"; format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_SUB => { RISCV_FP_SUB => {
name = "fsub"; format!("{}\t{}{}{}", "fsub.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_MUL => { RISCV_FP_MUL => {
name = "fmul"; format!("{}\t{}{}{}", "fmul.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_DIV => { RISCV_FP_DIV => {
name = "fdiv"; format!("{}\t{}{}{}", "fdiv.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_SQRT => { RISCV_FP_SQRT => {
name = "fsqrt"; format!("{}\t{}{}", "fsqrt.s", REG_F[rd], REG_F[rs1])
}, },
RISCV_FP_FSGN => { RISCV_FP_FSGN => {
match ins.funct3 { match ins.funct3 {
RISCV_FP_FSGN_J => { RISCV_FP_FSGN_J => {
name = "fsgnj"; format!("{}\t{}{}{}", "fsgnj.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_FSGN_JN => { RISCV_FP_FSGN_JN => {
name = "fsgnn"; format!("{}\t{}{}{}", "fsgnn.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_FSGN_JX => { RISCV_FP_FSGN_JX => {
name = "fsgnx"; format!("{}\t{}{}{}", "fsgnx.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
_ => name = "fsgn" _ => todo!("Unknown code")
} }
}, },
RISCV_FP_MINMAX => { RISCV_FP_MINMAX => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fmin"; format!("{}\t{}{}{}", "fmin.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else { } else {
name = "fmax"; format!("{}\t{}{}{}", "fmax.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} }
}, },
RISCV_FP_FCVTW => { RISCV_FP_FCVTW => {
if rs2 == 0 { if rs2 == 0 {
name = "fcvt.w.s"; format!("{}\t{}{}", "fcvt.w.s", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fcvt.wu.s"; format!("{}\t{}{}", "fcvt.wu.s", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FMVXFCLASS => { RISCV_FP_FMVXFCLASS => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fmv.x.w"; format!("{}\t{}{}", "fmv.x.w", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fclass.s"; format!("{}\t{}{}", "fclass.s", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FCMP => { RISCV_FP_FCMP => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fle.s"; format!("{}\t{}{}{}", "fle.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else if ins.funct3 == 1 { } else if ins.funct3 == 1 {
name = "flt.s"; format!("{}\t{}{}{}", "flt.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else { } else {
name = "feq.s"; format!("{}\t{}{}{}", "feq.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} }
}, },
RISCV_FP_FCVTS => { RISCV_FP_FCVTS => {
if rs2 == 0 { if rs2 == 0 {
name = "fcvt.s.w" format!("{}\t{}{}", "fcvt.s.w", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fcvt.s.wu" format!("{}\t{}{}", "fcvt.s.wu", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FMVW => { RISCV_FP_FMVW => {
name = "fmv.w.x"; format!("{}\t{}{}", "fmv.w.x", REG_F[rd], REG_F[rs1])
}, },
_ => name = "todo" _ => todo!("Unknown code")
} }
format!("{}\t{}{}{}", name, REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_SYSTEM => { RISCV_SYSTEM => {