use crate::decode::*;
use crate::print::*;

// doit disparaitre
const MEM_SIZE : usize= 4096;


pub struct Machine {
	pub pc : u32,
	pub int_reg : [u32 ; 32],
	pub instructions : [u32 ; 100],
	pub main_memory : [u8 ; MEM_SIZE],
	pub shiftmask : [u32 ; 32]
	// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
	//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
}


impl Machine {

	pub fn _init_machine() -> Machine {	
		let mut shiftmask : [u32 ; 32] = [0 ; 32];
		let mut value : u32 = 0xffff;

		value = (value << 16) + value;
		for i in 0..32 {
			shiftmask[i] = value;
			value = value >> 1;
		}

		Machine {
			pc : 0,
			instructions : [0 ; 100],
			int_reg : [0 ; 32],
			main_memory : [0 ; MEM_SIZE],
			shiftmask : shiftmask
		}	
	}


	/*
	execute the instructions table of a machine putted in param
	@param machine which contains a table of instructions
	*/
	pub fn run(machine : Machine){
		let mut m = machine;
		loop{
			Machine::one_instruction(&mut m);
		}
	}

	/*
	execute the current instruction
	@param machine which contains a table of instructions and a pc to the actual instruction
	*/
	pub fn one_instruction(machine :&mut Machine) {
	
		let mut unsigned_reg1 : u64 = 0;
		let mut unsigned_reg2 : u64 = 0;
		let mut long_result : i128 = 0;
		 
		 /*__int128 longResult;
  		int32_t localDataa, localDatab;
  		int64_t localLongResult;
  		uint32_t localDataaUnsigned, localDatabUnsigned;
  		int32_t localResult;
  		float localFloat;
  		uint64_t value;*/
	
		if machine.instructions.len() <= machine.pc as usize {
			println!("ERROR : number max of instructions rushed");
			return ;
		}

		let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
		
		machine.pc += 4;

		match inst.opcode {
			RISCV_LUI => {
				machine.int_reg[inst.rd as usize] = inst.imm31_12;
			},

			//******************************************************************************************
    		// Treatment for: OPI INSTRUCTIONS
			RISCV_OPI => {
				match inst.funct3 {
					RISCV_OPI_ADDI => {
						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32;
					},
					RISCV_OPI_SLTI => {
						machine.int_reg[inst.rd as usize] = 
							if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 };
					},
					RISCV_OPI_XORI => {
						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32;
					},
					RISCV_OPI_ORI => {
						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32;
					},
					RISCV_OPI_ANDI => {
						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32;
					},
					RISCV_OPI_SLLI => {
						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
					},
					RISCV_OPI_SRI => {
						if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize];
						} else { // SRAI
							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt);	
						}
					}
					_ => { println!("{} inconnu", inst.funct3); }
				}
			},
			
			RISCV_JAL => {
				machine.int_reg[inst.rd as usize] = machine.pc;
				machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u32);
			},
			
			RISCV_OP => {
				if(inst.funct7 == 1){
					match inst.funct3 {
						RISCV_OP_M_MUL => {
							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
							machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32;
						},
						RISCV_OP_M_MULH => {
							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
												
						},
						RISCV_OP_M_MULHSU => {
							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
            						long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
            						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u32;
						},
						// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
						/*
						* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
						* WHAT DA HECK
						*/
						RISCV_OP_M_MULHU => {
							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
            						unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
            						long_result   = (unsigned_reg1 * unsigned_reg2) as i128;
	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u32;
						},
						RISCV_OP_M_DIV => {
							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);
						}
						_ => {
							println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
						}
					}
				} else {
					match inst.funct3 {
						RISCV_OP_ADD => {
						// RISCV_OP_ADD_ADD inaccessible
							/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
							//}
						},
						RISCV_OP_SLL => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
						},
						RISCV_OP_SLT => {
							if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
							machine.int_reg[inst.rd as usize] = 1;
							} else {
							machine.int_reg[inst.rd as usize] = 0;
							}
						},
						RISCV_OP_SLTU => {
							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
							if unsigned_reg1 < unsigned_reg2 {
								machine.int_reg[inst.rd as usize] = 1;
							} else {
								machine.int_reg[inst.rd as usize] = 0;
							}
						},
						RISCV_OP_XOR => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
						},
						RISCV_OP_SR => {
						// RISCV_OP_SR_SRL inaccessible
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
						},
						RISCV_OP_OR => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
						},
						RISCV_OP_AND => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
						},
						_ => {
							println!("RISCV_OP undefined case\n");
						}
					}//LA
				}
			},
			//******************************************************************************************
    		// Treatment for: OPW INSTRUCTIONS
			RISCV_OPW => {
				if inst.funct7 == 1 {
					let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
					let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;

					// Match case for multiplication operations (in standard extension RV32M)
					match inst.funct3 {
						RISCV_OPW_M_MULW => {
							machine.int_reg[inst.rd as usize] = localDataa * localDatab;
						},
						RISCV_OPW_M_DIVW => {
							machine.int_reg[inst.rd as usize] = localDataa / localDatab;
						},
						RISCV_OPW_M_DIVUW => {
							machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned;
						},
						RISCV_OPW_M_REMW => {
							machine.int_reg[inst.rd as usize] = localDataa % localDatab;
						},
						RISCV_OPW_M_REMUW => {
							machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned;
						},
						_ => {
							println!("this instruction ({}) doesn't exists", inst.value);
						}
					}
				} else {
					let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;

					// Match case for base OP operation
					match inst.funct3 {
						RISCV_OPW_ADDSUBW => {
							if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
								machine.int_reg[inst.rd as usize] = localDataa + localDatab;
							} else { // SUBW
								machine.int_reg[inst.rd as usize] = localDataa - localDatab;
							}
						},
						RISCV_OPW_SLLW => {
							machine.int_reg[inst.rd as usize] = localDataa << (localDatab & 0x1f);
						},
						RISCV_OPW_SRW => {
							if inst.funct7 == RISCV_OPW_SRW_SRLW {
								machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f) & machine.shiftmask[32 + localDatab as usize];
							} else { // SRAW
								machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f);
							}
						},
						_ => {
							println!("this instruction ({}) doesn't exists", inst.value);
						}
					}
				}
			}
			_ => { println!("{} opcode non géré", inst.opcode)},
		}


	}
}

#[cfg(test)]
 mod test {
 	use super::Machine;
 
 }