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Remove ~60 warnings

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This commit is contained in:
Quentin Legot
2022-11-16 15:48:46 +01:00
parent f9dba1ac11
commit 9a233f3c12
3 changed files with 123 additions and 120 deletions
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26
src/machine.rs
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@@ -1,7 +1,7 @@
use crate::decode::*;
use crate::print::*;
//doit disparaitre
// doit disparaitre
const MEM_SIZE : usize= 4096;
@@ -9,7 +9,7 @@ pub struct Machine {
pub pc : u32,
pub int_reg : [u32 ; 32],
pub instructions : [u32 ; 100],
pub mainMemory : [u8 ; MEM_SIZE]
pub main_memory : [u8 ; MEM_SIZE]
// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
}
@@ -23,16 +23,16 @@ impl Machine {
pc : 0,
instructions : [0 ; 100],
int_reg : [0 ; 32],
mainMemory : [0 ; MEM_SIZE]
main_memory : [0 ; MEM_SIZE]
}
}
pub fn oneInstruction(mut machine : Machine) -> Machine {
pub fn one_instruction(mut machine : Machine) -> Machine {
let mut unsignedReg1 : u64 = 0;
let mut unsignedReg2 : u64 = 0;
let mut unsigned_reg1 : u64 = 0;
let mut unsigned_reg2 : u64 = 0;
if (machine.instructions.len() <= machine.pc as usize) {
if machine.instructions.len() <= machine.pc as usize {
println!("ERROR : number max of instructions rushed");
return machine;
}
@@ -69,6 +69,7 @@ impl Machine {
RISCV_OPI_SLLI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
}
_ => { println!("{} inconnu", inst.funct3); }
}
},
@@ -90,16 +91,16 @@ impl Machine {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_SLT => {
if(machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize]){
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_SLTU => {
unsignedReg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsignedReg2 = machine.int_reg[inst.rs2 as usize] as u64;
if(unsignedReg1 < unsignedReg2){
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
@@ -122,7 +123,8 @@ impl Machine {
println!("RISCV_OP undefined case\n");
}
}
},
}
_ => { println!("{} opcode non géré", inst.opcode)},
}